Part Number: AM62A7
I would like to receive a verification response regarding the validity of GIC interrupt map for AM62Ax included in Table 10-14 in SPRUJ16B document (AM62Ax TRM).
At my company I'm currently working on some IPC code requiring Mailbox peripheral usage. I got into some problems while trying to launch interrupts on A53 and did a little research on different implementations. I have found out that TI's Linux DTS for the SOC (https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi?h=ti-linux-5.10.y) differs in Mailbox interrupt number assignment compared to the TRM. For a 3rd reference, the MCU+ SDK for AM62A is also using vector numbers from TRM inside IPC drivers/examples (ipc_notify_v0_cfg.c)
| TRM GIC ID | DTS GIC ID | |
| Mailbox 0 | 108 | 76 |
| Mailbox 1 | 109 | 77 |
| Mailbox 2 | 140 | 108 |
| Mailbox 3 | 141 | 109 |
My code started working after switching to the DTS defined numbers, which makes me think that there could be an error both in TRM and MCU+ SDK.
I would appreciate your feedback on this issue as well as confirmation whether all other information included in TRM chapter 10 "Interrupts" is correct, including full GIC map and other subsystems data (MCU, MAIN, WKUP).
Regards,
Krzysztof
