AM6442: Configure ENT1 PORT to 100Mbps

Shine

Part Number: AM6442
Other Parts Discussed in Thread: DP83826E

Hello Champs,

HW: PHY 83826E
SW: mcu_plus_sdk_am64x_09_00_00_31

Hardware connection:

CPSW MAC ENT PORT1 is connected to 83826E as RMII SLAVE MODE, external crystal 50M is connected AM6442 to AA5 pin (i.e. RMII_MHZ_50_CLK) and 83826 pin 9

Testing:

By reading the PHY register 0x468, it shows that the PHY is operating with RMII SLAVE MODE, and read the register 0x10, he PHY is in the 100M full-duplex link state.

Problems encountered:

Forward data to ENT PORT1 via CPSW CPPI for Ethernet frame data transmission. Use the oscilloscope to catch PHY Chip Pin 23 (TXEN) PHY Chip Pin 24 (TXD0) PHY Chip Pin 25 (TXD1) and see the Ethernet Frame Preamble, Destination Address, Source Address, Random data, CRC (total 82 bytes), TXEN pulse width 65.6us, i.e. speed 10Mbps.

Customer guesses the ENT PORT1 sends only 10M. But he couldn't find the right configuration to change it to 100M.

The current CPSW speed-related configurations are as follows: (Are there any other configurations that can set the port speed?)

Set register (0x08022330) bit7 to 0:10/100 mode ; bit17 is 0: does not force into Gigabit

Customer is using the project based on C:\ti\mcu_plus_sdk_am64x_09_00_31\examples\networking\enet_layer2_cpsw\am64x-evm. The RGMII mode can run on EVM. But in the project and the hardware board, what is needed is the RMII mode, so he modified some of the configuration to fit the RMII mode.

①

SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, 1); //偏移量为4044，因此它落在分区1
*(vuint32_t*)(0x43004044) = 1; //cpsw0-port1 2选择RGMII 1选择RMII

*(vuint32_t*)(0x43004048) = 1; //cpsw0-port2 2选择RGMII 1选择RMII

SOC_controlModuleLockMMR(SOC_DOMAIN_ID_MAIN, 1);

② set (0x08022330) bit7 为 0:10/100 mode ; bit17 为 0:不强制进入千兆

③ configure RMII:

Thanks
Regards
Shine

7 months ago

0 Ashwani Goel 7 months ago

TI__Mastermind 20390 points

Hi Shine,

Thanks for your query.

Which SDK example you are referring here?

Best Regards

Ashwani

0 Shine 7 months ago in reply to Ashwani Goel

TI__Genius 13655 points

Hi Ashwani,

Thank you very much.

Customer is using the project based on C:\ti\mcu_plus_sdk_am64x_09_00_31\examples\networking\enet_layer2_cpsw\am64x-evm.

Thanks
Regards
Shine

0 Ashwani Goel 7 months ago in reply to Shine

TI__Mastermind 20390 points

Hi Shine,

Shine said:
C:\ti\mcu_plus_sdk_am64x_09_00_31\examples\networking\enet_layer2_cpsw\am64x-evm.

Can you ask customer to build example in debug mode and share UART logs ?

Best Regards

Ashwani

0 Shine 7 months ago in reply to Ashwani Goel

TI__Genius 13655 points

Hello Ashwani,

Thank you very much .

Below is the reply from customer.

Hello, I don't have a log on my side. Here's why: I'm based on C:\ti\mcu_plus_sdk_am64x_09_00_31\examples\networking\enet_layer2_cpsw\am64x-evm for this project. All relevant register configurations and DMA configurations were copied. In conjunction with the manual, complete a CPSW driver code generated without syscfg that is validated on the EVM board for RGMII Gigabit transceivers; Currently trying to configure the driver code to RMII mode, it was found that the speed was 10Mbps and could not be set to 100Mbps. No logs are provided as it is a self-written driver code.

But I can provide the register value of the CPSW related statistical count when there is a problem (only 10M):

/*CPPI Normal number of frames received */ *(int*)0x0803a000 = 958

/*CPPI Received Broadcast Frames */ *(int*)0x0803a004 = 958

/*CPPI Number of 65-127 frames received and sent */ *(int*)0x0803a06c = 958

/*CPPI Total bytes received and transmitted */ *(int*) (0x0803a080) = 70892

/*port 1 Number of Fragment Frames Received */ *(int*)0x0803a224 = 741

/*port 1 good frames sent */ *(int*)0x0803a234 = 958

Number of good frame broadcasts sent by /*port 1 */ *(int*)0x0803a238 = 958

/*port 1 bytes of all good frames sent */ *(int*)0x0803a264 = 70892

/*ENET TX Priority 0 Packet Count */ *(int*)0x0803a380 = 958

/*ENET TX Priority 0 Total bytes */ *(int*)0x0803a3a0 = 70892

The Ethernet frame data is populated as follows: (70 bytes, excluding CRC and preamble)

Tx_buffer[0][0] = 0xff;
Tx_buffer[0][1] = 0xff;
Tx_buffer[0][2] = 0xff;
Tx_buffer[0][3] = 0xff;
Tx_buffer[0][4] = 0xff;
Tx_buffer[0][5] = 0xff;
Memcpy&tx_buffer[0][6],macAddr,6);

Memset&tx_buffer[0][12],1,70-12);

In order to avoid any missed communication, I would like to repeat the main question: How to make RMII work in 100M mode.

Here is a screenshot of the TRM: I couldn't find a suitable operation for the RMII to operate in 100M mode.

After I configured the PHY to 10M, the PC can grab the transmitted frame: It is really the Ethernet frame that I sent in the MCU, here should be the table name PHY configuration should be fine, the only problem is why the RMII of CPSW works in 10M mode.

Thanks
Regards
Shine