• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 545 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM4372: mcSPI-Configuration

Alex Paul
Expert 6106 points

Part Number: AM4372

Dear experts,

I want to use 2x AM437x in my design.

To create some kind of Synchronization between those I would like to use the mcSPI-Interface.

My idea envisages using the 4xSPI Interface in half-duplex mode. 

2-SPI interfaces shall be used as receive only slave and two senders on both sides as Master in transmit Only mode.

Both sides should buffer up to 64 byte with the help of the FIFO. Both on receiver and transmitter side.

My assumption is that a separate FIFO is available for each SPI interface. Is that correct?
Is this configuration feasible or there are hardware restrictions in this regard that you see ? 

Regards,

Alex

  • 0
    TI__Guru**** 226955 points

    Hello Alex,

    Thank you for the query.

    Alex Paul said:
    My assumption is that a separate FIFO is available for each SPI interface. Is that correct?

    Please point me to the section you are referring.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Expert 6106 points

    Hi Sreenivasa,

    I am refering to the McSPI interface.

    The Fifo is mentioned in the TRM: 

    26.3.2.1 Dedicated Resources Per Channel

    Which would make me assume that it is available for any channel.

    Also this is described in

    26.3.2.4 Master Transmit-Only Mode

    were it is mentioned : 

    The built-in FIFO is available in this mode and can be configured with FFEW bit field in the MCSPI_CH(i)CONF register, then the FIFO is seen as a unique 64-byte buffer

    However  within the TRM the following note is mentioned a couple of times: 

    "Note: When more than one channel has an FIFO enable bit field (FFER or FFEW) set, the FIFO will not be used on any channel. Software must ensure that only one enabled channel is configured to use the FIFO buffer."

    Thus it would be nice to know if there is a dedicated FiFo for every McSpi Channel or if there is just one fifo that can be assigned to 1 channel.

    Regards,

    Alex

  • +1 in reply to Alex Paul
    TI__Guru**** 226955 points

    Hello Alex,

    Thank you.

    Please refer below inputs from the expert:

    Each McSPI instance has a 64-byte FIFO that can be used by only one (selectable) channel.  The FIFO will be 64-byte if the channel is configures as RX only or TX only,  it will be equally split if the channel is bi-directional.

     The customer’s proposed setup should work.

    Additional inputs: Seem excessive to use 4/5 SPIs for this.

    Regards,

    Sreenivasa