Other Parts Discussed in Thread: TMS320VC5506
Is there any documentation, sample code, or other support illustrating how to implement isochronous USB functionality on the C5506 without using the USB DMA?
My plan is to convert USB_postTransaction() from DMA to non-DMA for my ISO IN endpoints. The source for the USB CSL is available, and I can see how EP0 (IN and OUT) are implemented without DMA because they are limited to non-DMA mode only. It seems that the only step needed to ready a non-DMA transaction on EP0 is to write a non-zero byte count to the CT register (after copying the packet data to the ioport USB buffer space, of course). Unfortunately, the remaining endpoints have multiple registers for byte count when in isochronous mode, and thus one needs to update both CTX and CTXH.
I have already studied SPRU596A (USB Module), SPRU511 (USB CSL), and SPRS375C (TMS320VC5506), among others, and find that these few pieces of information are missing.
1) Does it matter what order CTX and CTXH are updated? Does one of them serve as a trigger, such that the other one should be loaded first? ... or does the USB host token act as a trigger such that the register order is not important? Even still, I would think that there is a race condition here where a host token may arrive between the update of CTX and CTXH.
2) Does CTXH/CTX count down to zero while the USB module transfers the data, such that it would be expected to be 0x000 at the end of the previous endpoint transaction? Further, am I correct in assuming that the action of writing a non-zero value to these registers will signal to the USB module that new data is available?
3) How would a 0-byte packet be sent manually, without USB DMA? Can I write a 0x000 to these CTXH/CTX registers and thus prepare the USB module for a valid 0-byte isochronous packet after the next SOF?
4) Is there any other USB endpoint register that I should update in isochronous mode to signal that data is ready? I assume from the non-DMA EP0 Control Endpoint source code that no such additional register access is needed (unless I missed it), but I cannot be sure that this necessarily means that the isochronous endpoints do not have an extra flag bit compared to the EP0 registers.
5) Most of the documentation states that CTY is not used for isochronous endpoints because DATA1 toggling is not active. Is this correct? Is CTY and the DATA1 buffer never used? Some pieces of documentation imply that DATA0 is always used to "start" an isochronous transfer, but that DATA1 and DATA0 alternate for additional transactions in a transfer. I can't quite find the relevant sections in the USB Specification for this, so I can't quite figure out whether DATA1 and the Y-Buffer would be seldom used or never used for isochronous endpoints.
6) At this time, I do not need to implement ISO OUT endpoints, so my priority is to obtain support for ISO IN. If your answer happens to also include non-DMA operations for ISO OUT then I'm sure the community would welcome the complete documentation.
P.S. I am working with the C5506 and see problems with non-USB DMA channel sync drop events when using a pair of isochronous endpoints. Each endpoint has a 1 ms update and a maximum packet size of 388 bytes. These endpoints nearly always transmit 386 bytes per packet except for the occasional 0-byte packet. The DSP is running at 108 MHz and 4 other DMA channels are active. The DMA channel which is dropping sync is triggered by the Timer at 4 MHz, transferring a single 16-bit word from SARAM to EMIF on each sync event. My hunch is that the USB DMA is operating in burst mode and therefore sometimes lasts long enough to block the 4 MHz DMA channel long enough for a 4 MHz Timer sync event to be dropped. This drop is affecting the signal integrity for the waveforms that I am generating via that DMA channel, and thus I absolutely must stop the USB DMA from causing problems.
