Hi,
As per errata, DDR3 requires s/w leveling instead of h/w due to silicon bug. Current s/w leveling works with the DDR3 used in EVM (EDJ1108DBSE part).
But we would use different chip than this for our designed h/w.
As I understand, I just need to change EMIF_TIM1, EMIF_TIM2,EMIF_TIM3, EMIF_SDREF, EMIF_SDCFG and EMIF_PHYCFG registers as per new DDR' page size, row/column address, timings etc.
I don't need to change any of the PHY control registers, even there are some hacks with "HACK_EYE_TRAINING" variable, which should work straight away for any other DDR3 chip.
Is my above understanding correct ? Or we need to fine tune PHY control registers as well ?
Thanks in advance.
Best Regards,
Sweta
