Other Parts Discussed in Thread: SYSCONFIG
I want to use the camera ISP in parallel sync mode without any resizers filters etc. I configured everything and I get an event (HS_VS_IRQ), but no interrupt was called (and no data was written to memory). I am pretty sure the my interrupt was configured correctly due I tested this with a timer. Hereby my code. I hope someone could help me with it:
// Reset globals
fb_ready = -1; // unassigned
fb_input = 0; // start filling buffer #0 below
// Disable CCDC, as some registers cannot be programmed unless the module is disabled
*CCDC_PCR = 0x00000000;
// Set the clocks for the Camera ISP module
*CM_CLKSTCTRL_CAM = 0x00000002; // Wake from sleep
*PM_WKDEP_CAM = 0x00000016; // Enable wake-up domain (both IVA and MCU)
// DPLL4 = (SYCLK/2) x 2 x M/N + 1 => 13 x 2 x 432/12 + 1 = 864 MHz
*CM_CLKSEL_CAM = 0x00000004; // cam_mclk = 216 MHz(864 / 4 = 216 MHz)
*CM_FCLKEN_CAM = 0x00000001; // enable cam_fclk/cam_mclk
*CM_ICLKEN_CAM = 0x00000001; // enable cam_iclk
*CM_SLEEPDEP_CAM = 0x00000000; // not in MPU mode
*PM_PWSTCTRL_CAM = 0x00000003; // powerstate = on
// CAM domain clock status ok?
while( !(*CM_CLKSTST_CAM & 0x00000001) ) {
TSK_sleep(1);
LOG_printf(&DEBUG, "Waiting for CAM clock domain");
}
// Wait until ISP reset is done
ISP_SYSCONFIG = 0x00001002; // standby = never, perform a software reset
while( !(ISP_SYSSTATUS & 0x00000001) ) {
TSK_sleep(1);
LOG_printf(&DEBUG, "Waiting for ISP");
}
// Enable INT15 configured by the DSP/BIOS
// The IE flag has not been set!
C64_enableIER(C64_EINT15);
// Set-up the camera ISP
// configure interrupts
// - disable all interrupts to the MCU (ARM)
// - enable VSync interrupt
// The address for the next buffer is loaded (by the CCDC module)
// on the vertical sync; the ISR sets the address for the _next_
// buffer, which will be loaded by the subsequent VSync interrupt
ISP_IRQ0ENABLE = 0x00000000;
ISP_IRQ1STATUS = 0xFFFFFFFF; // Clear all possible pending interrupts
ISP_IRQ1ENABLE = 0x80000000;
// timing control (required for the shutter, red-eye removal, etc.)
TCTRL_CTRL = 0x00000000;
TCTRL_FRAME = 0x00000000;
// set up circular buffer (transparent mode)
CBUFF_IRQENABLE = 0x00000000;
CBUFFx_CTRL[0] = 0x00000000; // disable both circular buffers
CBUFFx_CTRL[1] = 0x00000000; // disable both circular buffers
CBUFF_VRFB_CTRL = 0x00000000;
// disable all other features/submodules of the Camera ISP
CCP2_CTRL = 0x00000000;
CCP2_SYSCONFIG = 0x00000000;
CCP2_LC01_IRQENABLE = 0x00000000;
CCP2_LC23_IRQENABLE = 0x00000000;
HIST_PCR = 0x00000000;
H3A_PCR = 0x00000000;
PRV_PCR = 0x00000000;
RSZ_PCR = 0x00000000;
CSI2A_CTRL = 0x00000000;
CSI2A_SYSCONFIG = 0x00000000;
CSI2A_IRQENABLE = 0x00000000;
CSI2C_CTRL = 0x00000000;
CSI2C_SYSCONFIG = 0x00000000;
CSI2C_IRQENABLE = 0x00000000;
// clear SBL errors
SBL_PCR = 0x07FF0000;
// set up the control register
// - Select parallel port as input port (PAR_SER_CLK_SEL=0, PAR_BRIDGE=0)
// - Sample data on the rising edge of cam_pclk (PAR_CLK_POL=0)
// - Do not shift the data (SHIFT=0)
// - Enable CCDC
// - Enable CBUFF autogating feature
// - Disable H3A, HIST, PRV, RSZ submodules
// - Set SYNC_DETECT to VSync falling edge for interrupt
// - All other features are disabled
ISP_CTRL = 0x00018300;
// set up CCDC
// - set WENLOG (mostly because the Linux driver does so)
// - set VDLC
CCDC_CFG = 0x00000100;
// - select SYNC mode, HS, VS and FLD (not used) are inputs
// - polarity: active low (negative)
// - 10-bit data
// - module accepts raw input data, w/o filtering and what not
// - set internal timer generator to sync with VSync and HSync
// - enable writes to memory
CCDC_SYN_MODE = 0x0003060C;
// Set horizontal offset (when 0 each line will be overwritten)
CCDC_HSIZE_OFF = 0x0000A000; // 1280 pixels 32
// set initial address
CCDC_SDR_ADDR = (Uint32)(&(framebuffer[fb_input]));
// Pixels/lines to mem
CCDC_HORZ_INFO = 0x000004FF; // 1279 + 1 pixels to memory
CCDC_VERT_LINES = 0x000003FF; // 1023 + 1 lines to memory
// clear pixels offsets
CCDC_HSIZE_OFF = 0x00000000;
CCDC_VERT_START = 0x00000000;
// disable all other features
CCDC_CULLING = 0xFFFF00FF; // default values: retain all pixels
CCDC_SDOFST = 0x00000000;
// disable all other features of the CCDC
CCDC_CLAMP = 0x00000000;
CCDC_ALAW = 0x00000000;
CCDC_FMTCFG = 0x00000000; // disable PREVIEW, H3A and HIST
CCDC_LSC_CONFIG = 0x00000000; // disable lens-shading compensation
// set intterrupt
CCDC_VDINT = 0x04000000; // VDINT0 After 1024 + 1 lines, VDINT1 after 0 lines (not enabled)
// enable CCDC (can only be done after it has been configured)
CCDC_PCR = 0x00000001;
Best regards,
RS
