AM6442: How to configure SERDES0_REFCLK as an output and route internal PCIe reference clock to them?

Hi David,

Please try the following kernel patch.

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index c29864b3b0e7..4014d80dfae6 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -752,7 +752,7 @@
                        clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
                        clock-names = "refclk", "phy_en_refclk";
                        assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
-                       assigned-clock-parents = <&k3_clks 162 1>, <&k3_clks 162 1>, <&k3_clks 162 1>;
+                       assigned-clock-parents = <&serdes_refclk>, <&serdes_refclk>, <&serdes_refclk>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #clock-cells = <1>;

Hi Bin Liu,

The device tree change had no effect. We are using an older kernel from SDK 08.02.00.006. I do wonder if something has changed in the drivers that might affect this. We have a kernel upgrade in our backlog, and will report back whether that solves it.

Thanks and best regards

Hi David,

I don't think the kernel version matters that much.

Let me review this next week and get back to you. I don't work on PCI very frequently and don't remember all the details.

Hi David,

Sorry for my late response.

Please ignore my previous patch, it sets the SerDes REFCLK pins as input get clock from the PICe bus.

The AM64x kernel device tree by default should already set the SerDes REFCLK pins as output. Do you observe the 100MHz clock on the pins on AM64x GPEVM?

Hi Bin,

Bin Liu said:

The AM64x kernel device tree by default should already set the SerDes REFCLK pins as output. Do you observe the 100MHz clock on the pins on AM64x GPEVM?

you have to be careful there. Only the "E2" revision of the GPEVM had the RefClk pins connected directly between AM64x and the PCIe slot. Later revisions and the TMDS64EVM (there's only a "C" revision I believe) have a clock generator that sources the clock both to the AM64x (which should configure its pins as an input) and the PCIe slot.

That said, I'm not really sure what the Linux kernel driver does, because I worked mostly with MCU+ SDK on PCIe. Hardware-wise the configuration of the SerDes controller determines whether the RefClk pin acts as an input or as an output.

Regards,

Dominic

Hello Bin,

Thanks for your reply. I'm checking on the revision of our EVM and will get back to you, but based on Dominic's reply I'm not so hopeful. And in any case we have a custom AM64x-based board, although the EVM could be useful for testing the pin setup.

Hello Dominic,

I can certainly dive into the kernel code and find out how it's configuring the SerDes. However, I can't find any documentation for the SerDes registers, so I don't know what to look for, or if I find it, what values to expect. At least I found nothing in the TRM. Do you have any suggestions here? Given proper documentation, we have the necessary resources/know-how to sort out the kernel code.

Thanks and warm regards

Hello David,

you can modify an EVM (Rev. A+) to directly connect the RefClk pins from the AM64x to the PCIe slot. These are assembly options and you just need to resolder some 0 Ohm restistors.

You could look at the MCU+ SDK code to see how that configures RefClk for input or output:

https://github.com/TexasInstruments/mcupsdk-core/blob/next/source/drivers/hw_include/serdes_cd/V1/V1_1/csl_serdes3.c#L421

(note that on the current version only the SerDes code is prepared to handle different RefClk options. The PCIe driver that builds upon the SerDes code unconditionally configures RefClk as an output)

You should be able to locate similar code in the kernel, so that you can verify how the SerDes RefClk is configured.

Regards,

Dominic