• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 99 subscribers
  • Views 481 views
  • Users 0 members are here
Support feedback
Options
Options

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM62A3: DDR layout guidelines vs AM62A EVM

Gunter Schmer
Genius 14222 points
Part Number: AM62A3

Hi all,

a customer has the following urgent questions:

  1. The AM62Ax DDR Board Design Guidelines does not mention the ODT0/1 pins in the LPDDR4 interface. Is the CA ODT controlled exclusively through the MRs?
  2. Why is the DDR routing length matching constraints in the AM62A EVK so much tighter than the specs in the DDR Board Design and Layout Guidelines document?  Can the customer use a constraint of 3mm per the datasheet?

Thanks!

--Gunter

  • 0
    TI__Guru* 86570 points

    Gunter,

    1. ODT0/1 signals on AM62Ax are not used for LPDDR4 (these would be eventually used for a DDR4 interface if/when it is supported).  On the memory side, there are ODT_CA signals which should be pulled high to VDD2 (see schematic diagrams in the app note).  ODT_CA can be exclusively disabled using MR22, and there is a selection in the DDR Registers Config Tool to choose either mode

    2. The EVM was designed before first silicon with tighter constraints, and at the time when we did not realize the flexibility of the delay elements in the PHY.  We just recently relaxed the length matching constraints in the app note to facilitate layout for customers.   I would still recommend to match these as tight a possible for their design.  I don't know which parameter for 3mm they are referring to.  Note that all of the length matching specs are in ps, to emphasize matching the propagation delays, in which the length of the trace on one component.

    Regards,

    James

  • 0 in reply to JJD
    TI__Prodigy 690 points

    Hey James, is it okay to reference the DDR signals to VDDQ/VDDS_DDR? The layout guidelines only mentions referencing VSS but normally it is also acceptable to reference the positive IO rail as long as the trace does not cross any splits.

  • 0 in reply to Cal Muckelbauer
    TI__Guru* 86570 points

    Hi Cal, for AM62A, our requirement would be reference to ground.  I talked with one of our sim experts, and at the max frequencies that AM62A supports, he does not recommend trying to reference the signals to the power plane.  

    Regards,

    James

  • 0 in reply to JJD
    TI__Prodigy 690 points

    Hey James. Can you elaborate on this requirement, is there data to show why we shouldn't be referencing to VDDQ/VDDS_DDR? Amazon is pushing back because they have a 10 layer board and it would be difficult for them to only reference ground. 

    Is referencing ground more of a suggestion from us? If they simulate and show it works referencing VDDQ/VDDS_DDR, can they move forward doing this?

  • 0 in reply to Cal Muckelbauer
    TI__Guru* 86570 points

    Cal, this is coming from our sim experts here.  They would not recommend referencing to the power plane for the frequencies that AM62A supports.  With that said, if the customer performs power aware board simulations with power plane as the reference, they can go that route.  It's not impossible to get it to work, just that our sim team recommends a ground reference plane for better chances for a successful design.  

    I don't have the history on this recommendation, if they want more depth, we'd have to follow up with folks from our sim team, which could not happen until next week.

    Regards,

    James