TDA4VM: How to improve valid data in one cycle on cistx node.

Hi TI experts,

i use linux SDK8.4 on TDA4VM platform.

Now i use csitx to send data to display end. the resolution is 2560*1440. i hope fps is 25.

i find that it cannot display well on display end. 

The same serializer on other platform with the same resolution is no problem.

The Max bps is 3Gbps on this serializer. it overflow when i send  2560*1440 data with 25 fps on TDA4EVM platform. 

but it is less then 3Gbps on other platform.

i test the wave on board and find the problem.

on TDA4EVM platform the duty ratio of valid data is lower than other platform.

so it need to more bandwidth when send the same valid data.

This is the wave as below.

other platform:  duty ratio = 37ms/40ms = 0.925

TDA4EVM platform:  duty ratio = 25ms/40ms = 0.625

How to improve  valid data duty ratio on TDA4EVM platform?

Can i reduce the blank on csitx node? i find vBlank and hBlank value on this function. how to set it less then now?

Is there anything to reduce invalid data in csitx node.

void tivx_csitx_params_init(tivx_csitx_params_t *prms)
{
uint32_t cnt, loopCnt;

if (NULL != prms)
{
    prms->numInst = 1u;
    prms->numCh = 0u;

    ...

    prms->instCfg[loopCnt].vBlank = 22U;
    prms->instCfg[loopCnt].hBlank = 40U;
    prms->instCfg[loopCnt].startDelayPeriod = 40U;

   ...

}

Best Regards