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PROCESSOR-SDK-AM64X: MPU_INIT

Jun Tu
Expert 1620 points
Part Number: PROCESSOR-SDK-AM64X
Other Parts Discussed in Thread: SYSCONFIG, TMDS64EVM

Hi

"In the generated code from sysconfig, I noticed some inconsistencies between the MPU interrupt configuration and its actual usage. Can you assist me in addressing this issue?

  1. "For UART, we have UART0 located at address 0x2800000. Should it be configured for both read and write access? Why is it configured as user read-only? I mean, users also need to write to UART for debugging purposes, correct?"

  2. "Additionally, if we want to configure Timer at address 0x2410000, it should also be set for user read and write access, right? Why is it not configured anywhere?"

  3. "If register access privilege is not configured in the MPU, what will be the default behavior?

    Thanks.

<generated code>

const MpuP_RegionConfig gMpuRegionConfig[CONFIG_MPU_NUM_REGIONS] RODATA_CFG_SECTION =
{
    {
        .baseAddr = 0x0u,
        .size = MpuP_RegionSize_2G,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 0,
            .isBufferable = 0,
            .isSharable = 1,
            .isExecuteNever = 1,
            .tex = 0,
            .accessPerm = MpuP_AP_S_RW_U_R,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x0u,
        .size = MpuP_RegionSize_32K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_S_RW_U_R,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x41010000u,
        .size = MpuP_RegionSize_32K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_S_RW_U_R,
            .subregionDisableMask = 0x0u
        },
    },
</generated>
  • 0
    Expert 1620 points

    4. eg : in blelow photo ram reserved for DMSC, so both m3 (mcu) and main(cpu) will have access to that part of memory,

    however in ti gernerated code, why that area is not sharable and user read only mode.

        {
            .baseAddr = 0x70000000u,
            .size = MpuP_RegionSize_2M,
            .attrs = {
                .isEnable = 1,
                .isCacheable = 1,
                .isBufferable = 1,
                .isSharable = 0,
                .isExecuteNever = 0,
                .tex = 1,
                .accessPerm = MpuP_AP_S_RW_U_R,
                .subregionDisableMask = 0x0u
            },
        },

  • 0 in reply to Jun Tu
    TI__Guru 50737 points

    Hello Jun,

    Thanks for your question.

    Kindly allow me sometime to go through your problem statement.

    Regards,

    Vaibhav

  • 0
    TI__Guru 50737 points

    Hello Jun,

    Jun Tu said:
    For UART, we have UART0 located at address 0x2800000. Should it be configured for both read and write access? Why is it configured as user read-only? I mean, users also need to write to UART for debugging purposes, correct?"

    As far as UART0 is considered, we do have several registers in which some are meant for:

    1. Read only

    2. Write only

    3. Both Write and Read

    So accordingly you can find registers which demonstrate the same, for example, the UART_THR is meant for Writing purpose and on the other hand UART_RHR is meant for reading purpose and so on.

    Jun Tu said:
    "Additionally, if we want to configure Timer at address 0x2410000, it should also be set for user read and write access, right? Why is it not configured anywhere?"

    Are you talking about DM Timers here ?

    Please allow me sometime to get back on the reasoning behind READ and WRITE context. Please expect responses by today.

    Regards,

    Vaibhav

  • 0 in reply to Jun Tu
    TI__Guru 50737 points

    Hello Jun,

    I have a follow up question before I proceed with the debug.

    I am going to run an experiment where I am going to try to see the Program status registers by the help of which I can figure out if the mode while writing to a particular UART register is Supervisor or User Mode.

    For this I would like to know, do you want me to do this experiment on R5F or M4F.

    Looking forward to your response.

    Regards,

    Vaibhav

  • 0 in reply to Vaibhav Kumar
    Expert 1620 points

    on R5F please.  TMDS64EVM is the board that we are going to use. Thanks.  

    Reference. www.ti.com/.../TMDS64EVM

  • 0 in reply to Jun Tu
    TI__Guru 50737 points

    Hello Jun,

    Thanks for your quick response.

    Jun Tu said:
    on R5F please.  TMDS64EVM

    I am going to consider a R5F example then and I will make sure to test on TMDS64EVM.

    Regards,

    Vaibhav

  • +1 in reply to Jun Tu
    TI__Guru 50737 points

    Hello Jun,

    Post your response, I started actively working on this.

    So I ran a simple UART based application which writes to the UART FIFO.

    I did this to see in which mode of operation is the data written, Supervisor or User mode.

    Turns out it is Supervisor mode in which the Write operation is being performed to the UART registers.

    Please check the M bit or what we also call as Mode Bit value under the Registers tab in the attached IMAGE 2, the M Bit value shows 10011 which indicates Supervisor and 10000 indicates User mode of operation.

    IMAGE 1






    IMAGE 2

    Hopefully this clarifies that the write operation is mostly done in Supervisor mode.

    Let me know if this resolved your issue.

    Happy to help you.

    Regards,

    Vaibhav

  • 0 in reply to Vaibhav Kumar
    Expert 1620 points

    hI, Vaibhav:

    It is clear to me. Thanks