We are working on a J784s4 dev board, running some benchmarks in QNX. We have been trying to configure MSMC as L3 Cache, and have been running into some issues.
Some Background:
Board: J784s4
PDK 9.01.00.06
qnx710
Initially, We followed this guide to get our QNX Image: https://software-dl.ti.com/jacinto7/esd/processor-sdk-qnx-j784s4/09_01_00_06/exports/docs/build_steps_j784s4.html#build-steps-dev-platform
Our MSMC was configured with 0MB L3 Cache by default.
This documentation shows configuring K3 MSMC as L3 for the J721e platform: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j784s4/latest/exports/docs/linux/How_to_Guides/FAQ/How_to_Configure_MSMC_memory.html
This details modifying “.msmc_cache_size” in soc/j721e/evm/board-cfg.c. There was not an equivalent file for soc/j784s4, and this seems somewhat out of date.
We referred to documentation in pdk_j784s4_09_01_00_22/docs/userguide/j784s4/boot/boot.html and found that we needed to configure “.msmc_cache_size” in the sciclient.
We found the files:
- pdk_j784s4_09_01_00_22/packages/ti/drv/sciclient/soc/V6/sciclient_defaultBoardcfg.c
- pdk_j784s4_09_01_00_22/packages/ti/drv/sciclient/soc/V6/sciclient_defaultBoardcfg_rm.c,
and the script to update board config:
- pdk_j784s4_09_01_00_22/packages/ti/drv/sciclient/tools/boardcfg_update.sh
We were able to get 1MB of L3 Cache configured by updating the .msmc_cache_size to 0x01 in both defaultBoardcfg files as seen below, and running the boardcfg_update.sh script before building sbl:
/* tisci_boardcfg_msmc */
.msmc = {
.subhdr = {
.magic = TISCI_BOARDCFG_MSMC_MAGIC_NUM,
.size = (uint16_t) sizeof(struct tisci_boardcfg_msmc),
},
/* If the whole memory is X MB the value you write to this field is n.
* The value of n sets the cache size as n * X/32. The value of n should
* be given in steps of 4, which makes the size of cache to be
* configured in steps on X/8 MB.
*/
.msmc_cache_size = 0x01,
},
Trying to configure more than 1MB of L3 cache, we began running into issues. We attempted changing this .msmc_cache_size value to 0x08, 0x0f, 0x07, 0xff, etc.
All these attempted values kept the cache configured to 1MB or 2MB.
Questions:
Are we missing some configuration for the MSMC that is required? Or perhaps some other configuration is conflicting?
Is there any updated documentation for configuring MSMC on J784s4 with PDK 9.01.006?
Any information would be much appreciated.
