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Why is DDR init required over PCI for C6678 in PCIe boot?

Subhranil Choudhury77614
Prodigy 90 points

I have connected the C6678 EVM to a PC with the PC acting as RC and C6678 as EP. Only IBL is running on C6678.

I am using the "pciedemo" driver obtained with C6678 mcsdk from a Linux PC to transfer "Hello world" onto the C6678 over PCIe.

In the "pciedemo" module there is a line of code as "pushData(ddrInitCode, 0, &bootEntryAddr);".

I believe this piece of code is initializing the C6678 DDR.

Can somebody tell me why:

1. We need to externally initialize DDR of C6678 EVM externally over PCIe

2. Why is the bootloader not initializing the DDR in PCIe boot-mode?

  • 0
    TI__Mastermind 42545 points

    The initialization of the DDR3 registers requires some knowledge of the physical layout of the DDR3 traces.  Some of the initial values programmed into the registers are directly related to the length of the address traces.  Since these values will be different for every board it isn't possible to use the boot code in the C6678 to initialize the DDR3 interface. 

  • 0 in reply to Bill Taboada
    Prodigy 90 points

    Hi Bill,

    Thanks for the reply. 

    If i am not wrong, i feel you are referring to the ROM Boot-loader which resides the C6678 SOC.

    But, actually I feel i did not  quote the querry correctly.

    My doubt was that "Why is the IBL running on C6678 not initializing the DDR3 interface in case of PCIe boot-mode configuration?"

    I was just trying to understand the thought behind it as in Nand boot mode , DDR3 interface gets initialized in the IBL but not in PCIe boot-mode.

  • 0 in reply to Subhranil Choudhury77614
    TI__Intellectual 1485 points

    Hi Subhranil,

    PCIe boot is a ROM boot mode, the ROM boot loader does not initialize the DDR3. NAND boot is an I2C boot mode, the ROM boot loader will first boot IBL via I2C EEPROM, IBL does the DDR init and boots the application image from the NAND.

    Note:

    For ROM boot modes (SGMII, PCIe, SRIO, HyperLink, etc.), to workaround the PLL lockup issue (refer to C6678 errata document, February 2011, advisory 8), the RBL will boot the 1st stage IBL from I2C EEPROM which contains the PLL reset workaround and then re-enter RBL to continue the ROM boot. The 1st stage IBL does not initialize the DDR3. Please refer below link for details:

    http://processors.wiki.ti.com/index.php/BIOS_MCSDK_2.0_User_Guide#Booting_and_Flash

     

    Regards,

    Hao.

  • 0 in reply to Hao
    TI__Intellectual 895 points

    See the note in the IBL section (section 7.3) of the User Guide that Hao refers to above for the sequence:

    Note:

    For ROM boot modes (EMAC, SRIO, HyperLink, etc.) and I2C boot mode with bus address 0x50, to provide a workaround for the PLL lockup issue (refer to C6678 errata document, February 2011, advisory 8), the DSP will boot IBL from I2C EEPROM bus address 0x51 which contains the PLL reset workaround. Below are the steps done in the IBL:

    1. FPGA samples the bootmode pins
    2. FPGA forces the DSP to boot via I2C bus address 0x51
    3. PLL is initialized correctly by the IBL on the I2C.
    4. IBL reads the sampled bootmode from an FPGA register and writes this value into the DEVSTAT register
    5. IBL writes the Boot ROM entry address into the DSP Program Counter
    6. DSP executes the desired internal ROM boot mode or boot from I2C bus address 0x50 as normal

    Raj