Hi!
I've been trying to configure the Timer1 (not Timer0) to act as a watchdog. Since the Docs say one needs to set TIM34RS and TIM12RS i've started with code to accomplish this first. Having a JTAG debugger connected i see that the TIM12RS bit in TGCR (Timer Global Control Register).
See below for code i'm executing. Am i missing anything? I also tried setting the PLUSEN bit first with no effect.
TMR1->GPINT_GPEN = (1u << 17) | (1u << 16); // GPINTGPEN set GPENO12 | GPENI12
TMR1->GPDATA_GPDIR = (1u << 17) | (1u << 16); // GPDATGPDIR set GPDIRO12 | GPDIRI12
// stop and reset the timer
TMR1->TGCR = 0x00000000;
TMR1->TCR = 0x00000000;
TMR1->WDTCR= 0x00000000;
TMR1->INTCTLSTAT = 0; // disable interrupts
SETBIT(TMR1->EMUMGT, (0x01 << 0)); // set emulation to free run.
// set 64-bit watchdog mode
// remove from reset
// prescaler is 0
TMR1->TGCR = (TIMMODE_32BIT_UNCHAINED | TIM34RS | TIM12RS);
// clear counter registers, set period registers
TMR1->TIM12 = 0x00000000;
TMR1->TIM34 = 0x00000000;
TMR1->PRD12 = 0xFFFFFFFF;
TMR1->PRD34 = 0xFFFFFFFF;
// start timer1 - 1:2 and 3:4
SETBIT(TMR1->TCR, ENAMODE34_CONT | ENAMODE12_CONT);
