AM62A3: LPDDR4 DQS DQ BYTE class skew requirements

Hi Gunter, the PHY has several delay elements per DQ bit to accommodate for this skew, so during training, the propagation delay with be appropriately deskewed across the byte to ensure signals are aligned.  These specs were recently relaxed in this app note to facilitate customer designs.

AM64x is still strict as it has not gone thru revisions to relax the parameters.

Regards,

James

Hi James, does the 150ps skew specification refer to the skew within the byte from SoC DRAM pin to the DRAM internal latch, or if it pertains to the PCB trace only?

Thanks

Jun

Hi Jun, the skew refers to pin to pin.

Regards,

James  

Hi James,

Thank you for the clarification. Just to confirm my understanding, if the skew refers to pin-to-pin timing, then the 150ps timing constraint should not directly apply to our PCB trace matching requirements for layout design. Am I correct in assuming this? And is 150ps skew defined for the data bits within one byte?

Thanks

Jun

Jun, i apologize i gave some incorrect information earlier.  The skew is not only pin to pin.  Check note (4) in the table notes 

(4) Consider the delays from SOC die pad to the DRAM pin (ie. delays of SOC package + delays of PCB upto the DRAM pin. DRAM
package delays are omitted). Refer to Appendix: SOC Package Delays.

The package delays can be found in the appendix.  Your other question is addressed in note (6), yes skew is defined for DQx and DQSx associated with the byte

James   

Hi James,

thanks for the clarification. We understand that the 150ps skew specification across DQx & Bytex is recently released. To gain a deeper understanding of the rationale behind this change from the previous 2ps specification for AM64xx to 150ps, could you please elaborate on the factors that led to a skew specification of 150ps for AM62A3.

We did some analysis on timing margin breakdown for data rate 3733 as below:

1) The maximum skew between SoC die and the DRAM pin is 150ps, which translates to about 0.56 UI

2) Receiver eye opening requires 0.2UI

3) the remaining timing margin for the DRAM pin to reach the internal latch is 0.24 UI, this value typically falls below the recommended min requirements set by DRAM vendors

Could you please review our analysis and confirm if there are any discrepancies or misunderstandings on our end?

thanks

jun

Jun,

you are missing the adjustments made by the training steps performed during initialization.  Several training steps associated with read eye training and write DQ training will utilize slave delay elements in the PHY to align each byte appropriately, effectively nullifying any board trace length mismatch.  The PHY has per-bit deskew capability on both the read and write paths.  Thus it can apply delay elements on each signal within a byte to align signal transitions and capture points

Regards,

James 

Thanks, James. could you confirm whether this 150ps skew value has already been implemented and characterized on your reference board design? If possible, any relevant documentation or characterization reports related to achieving this skew level would be extremely helpful.

We understand there's a process for writing leveling and training for DDR memory. In this context, we'd like to inquire about the per-bit deskew range supported by AM62A3. This information will help us determine the overall achievable margin for reliable DRAM operation at the required data rate.

Thanks

Jun

Jun, we have not intentionally created a board with 150ps of skew.  These requirements are based on design specs from the DDR vendor.  Most of the documentation you are asking for is based off of internal vendor design specs, not sure if i can share those with customers.  I will follow up with Gunter.

Regards,

James

James, thank you for your follow-up and please confirm if the 150ps skew specification applies to the maximum allowable skew across the entire PCB, including SoC package, for the DQ signals.To ensure we're on the same page,  we're discussing LPDDR4 and not LPDDR3, as indicated in the title.

James, this information is crucial for finalizing our PCB design, can we get confirmation these two day?

Thanks

Jun

Yes, this is correct for DQ DQS of the same byte.  Note that it is recommended to keep DQS shorter than all the other DQx in the byte.  

Regards,

James