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TMDS64EVM: about ipc_rpmsg_echo sample project

Part Number: TMDS64EVM
Other Parts Discussed in Thread: SYSCONFIG

Hello TI support team.

I'm using mcu_plus_sdk_am64x_08_06_00_45.
I am checking the operation of IPC RPMsg with ipc_rpmsg_echo_am64x-evm_system_freertos_nortos.
However, CR50-0 uses freertos. I would like to change this to nortos and make it work.
Is it correct to just modify the following in main.c of CR5?

int main(void)
{
    /* init SOC specific modules */
    System_init();
    Board_init();

#if 0

    /* This task is created at highest priority, it should create more tasks and then delete itself */
    gMainTask = xTaskCreateStatic( freertos_main,   /* Pointer to the function that implements the task. */
                                  "freertos_main", /* Text name for the task.  This is to facilitate debugging only. */
                                  MAIN_TASK_SIZE,  /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
                                  NULL,            /* We are not using the task parameter. */
                                  MAIN_TASK_PRI,   /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
                                  gMainTaskStack,  /* pointer to stack base */
                                  &gMainTaskObj ); /* pointer to statically allocated task object memory */
    configASSERT(gMainTask != NULL);


    /* Start the scheduler to start the tasks executing. */
    vTaskStartScheduler();

#else
    // for nortos
    ipc_rpmsg_echo_main(NULL);
    for(;;){
        ;
    }
#endif

Best regards,

Kiyomasa Imaizumi.

  • I created an IPC RPMSG project from an empty project (CA53 and CR5).

    To realize CA53 and CR5 IPC RPMessage, ipc_rpmsg_echo.c from the ipc_rpmsg_echo sample was added to the empty project.
    However, CA53 and CR5 cannot be exited from RPMessage_getEndPtMsg of the RPMessage_recv function.
    Attach the empty project and waiting images.

    empty_am64x-evm_system_nortos.zip

    I think IPC RP Message is set correctly in sysconfig.

    I have no idea what's wrong.
    Could you please tell me the correct way to fix it?

    Best regards,

    Kiyomasa Imaizumi.

  • Hello Kiyomasa Imaizumi,

    Sorry for delayed response as I am on other customer escalations.

    Please check the below FAQ. It is helpful to port NORTOS IPC examples to FreeRTOS, and it was implemented long back .

    I hope this helps in your use case like porting NORTOS to FreeRTOS examples as well .If  you still faces any issues please let me know .

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1230201/faq-am6442-am64x-how-do-i-port-ipc-examples-to-rtos-projects-from-no-rtos-projects

    Regards,

    S.Anil.

  • Hello Swargam Anil

    Thank you for your reply.

    The MPU REGIN setting was missing in sysconfig, so I added it.
    After modifying it as shown below, building and running it, IPC RPmessage was realized on NORTOS.
    thank you.

    However, in the ipc_rpmsg_echo_main_core_start function on the MainCore (CR5) side, if gMsgEchoCount is 1000, it will succeed, but if it is around 10000, the process will freeze.
    Even if I put ClockP_usleep(1000) inside the for loop on the CR5 side as shown below, the problem was not resolved.

    void ipc_rpmsg_echo_main_core_start(void)
    {
        RPMessage_CreateParams createParams;
        uint32_t msg, i, numRemoteCores;
        uint64_t curTime;
        char msgBuf[MAX_MSG_SIZE];
        int32_t status;
        uint16_t remoteCoreId, remoteCoreEndPt, msgSize;
    
        RPMessage_CreateParams_init(&createParams);
        createParams.localEndPt = MAIN_CORE_ACK_REPLY_END_PT;
        status = RPMessage_construct(&gAckReplyMsgObject, &createParams);
        DebugP_assert(status==SystemP_SUCCESS);
    
        numRemoteCores = 0;
        for(i=0; gRemoteCoreId[i]!=CSL_CORE_ID_MAX; i++)
        {
            numRemoteCores++;
        }
    
        /* wait for all cores to be ready */
        IpcNotify_syncAll(SystemP_WAIT_FOREVER);
    
        ClockP_usleep(500*1000); /* wait for log messages from remote cores to be flushed, otherwise this delay is not needed */
    
        DebugP_log("[IPC RPMSG ECHO] Message exchange started by main core !!!\r\n");
    
        curTime = ClockP_getTimeUsec();
    
    //    for(msg=0; msg<gMsgEchoCount; msg++)
        for(msg=0; msg<10000; msg++)
        {
            snprintf(msgBuf, MAX_MSG_SIZE-1, "%d", msg);
            msgBuf[MAX_MSG_SIZE-1] = 0;
            msgSize = strlen(msgBuf) + 1; /* count the terminating char as well */
    
            /* send the same messages to all cores */
            for(i=0; gRemoteCoreId[i]!=CSL_CORE_ID_MAX; i++ )
            {
                status = RPMessage_send(
                    msgBuf, msgSize,
                    gRemoteCoreId[i], gRemoteServiceEndPt,
                    RPMessage_getLocalEndPt(&gAckReplyMsgObject),
                    SystemP_WAIT_FOREVER);
                DebugP_assert(status==SystemP_SUCCESS);
            }
            /* wait for response from all cores */
            for(i=0; gRemoteCoreId[i]!=CSL_CORE_ID_MAX; i++ )
            {
                /* set 'msgSize' to size of recv buffer,
                * after return `msgSize` contains actual size of valid data in recv buffer
                */
                msgSize = sizeof(msgBuf);
                status = RPMessage_recv(&gAckReplyMsgObject,
                    msgBuf, &msgSize,
                    &remoteCoreId, &remoteCoreEndPt,
                    SystemP_WAIT_FOREVER);
                DebugP_assert(status==SystemP_SUCCESS);
            }
            ClockP_usleep(1000); // <-- add code
        }
    

    Please tell me how to solve it.

  • Hello Swargam Anil

    additional information.
    Processing was not completed even though gMsgEchoCount was 1000.
    When I suspended CA53 and CR5, it stopped at the following point.


    Is there any waiting time required inside the for loop?
    It seems to be working fine in step execution.

    Best regards,
    Kiyomasa Imaizumi.

  •  

    Hello Kiyomasa Imaizumi, 

    Thanks, one problem s solved: porting examples from RTOS to NO RTOS. 

     

    The above comment on other issues is that your A53 core went into some handler state, and this should not have happened. 

     

    And one more thing is that in the above comments, you said that IPC is working for 1000 counts and not for 10000 counts. This is also not acceptable. 

     

    So, just try these steps if you use the same uart or any other peripheral in both cores. Uses them at once. 

     

    Next, generate a multicore app image for both cores and load them to external flash. See still if application running or or not. 

    Make sure that IPC memory MPU region has been configured in all cores  and linker files. 

     

    Regards, 

    S. Anil. 

  • Hello Swargam Anil
    Thank you for your reply.

    >So, just try these steps if you use the same uart or any other peripheral in both cores. Uses them at once.
    Please tell me about the above. Does this mean that common peripherals should not be used in both cores?
    I don't know what these steps mean, so please let me know.

    >Next, generate a multicore app image for both cores and load them to external flash. See still if application running or or not.
    >Make sure that IPC memory MPU region has been configured in all cores and linker files.
    Does this mean I should write the CA53 and CR5 applications to OSPI flash instead of booting to RAM from CCS and see if it works?

    Best regards,
    Kiyomasa Imaizumi.

  • Hello Swargam Anil.

    I tried booting CA53 and CR5 from OSPI flash.
    CR5 can output using UART0, and CA53 can output using UART1.

    However, like RAM startup, it does not end at 10000 counts. It ends at 1000 counts.
    I looked at linker.cmd, and the IPC area is taken up by both CPUs as shown below.
    Is something wrong?

    MEMORY
    {
        DDR : ORIGIN =  0x80000000, LENGTH = 0x2000000
    
        /* shared memory segments */
        /* On A53,
         * - make sure there is a MMU entry which maps below regions as non-cache
         */
        USER_SHM_MEM            : ORIGIN = 0x701D0000, LENGTH = 0x80
        LOG_SHM_MEM             : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
        RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
    }
    


    Best regards,
    Kiyomasa Imaizumi.

  • Hello Swargam Anil.

    I will attach you a project that implements ipc RPMsg based on empty project.
    In this project, CA53 will be the master and send RPMsg to CR5.

    Best regards,
    Kiyomasa Imaizumi.
    Ipc_rpmsg_empty.zip

  • Hello Swargam Anil.

    Is there any progress regarding IPC RPMsg processing not completing?

    Best regards,
    Kiyomasa Imaizumi.

  • Hello Kiyomasa Imaizumi.

    I have looked at your code, and it seems OK but I found the issues in MMU settings in A53 core for IPC.

    You can directly take an IPC example of A53 core and add your changes in this example. This is good to approach instead of adding changes in empty project.

    After that, try examples at your side. If it still is not working, I can check at my side. And share your updated examples if the examples are not working after the MMU changes to A53.

    Regards,
    S.Anil.