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AM620-Q1: NAND flash Management

Akshay Katare
Intellectual 435 points
Part Number: AM620-Q1

Hello,

We have following queries particularly for NAND flash memory

1)As per Boot process, SBL loads MCU image.So whether SBL has bad block management?

2)Whether chances of simultaneous access to memory by different cores is implicitly handled or we have to manage it explicitly (may be getting confirmation one core has completed it's access to memory)?

Regards,

Akshay

  • +1
    TI__Mastermind 44616 points

    Hello Akshay,

    Thanks for your question.

    Currently in the SDK, we are yet to implement bad block management.

    The schedule for this is SDK version 10.

    Akshay Katare said:
    2)Whether chances of simultaneous access to memory by different cores is implicitly handled or we have to manage it explicitly (may be getting confirmation one core has completed it's access to memory)?

    Can you briefly explain the usecase for me to be able to answer correctly?

    My initial go to would be IPC Notify Sync All mechanism to communicate among all initialized cores.

    Regards,

    Vaibhav