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Finding u-boot source file for setting OMAP_L138 EMIF3 DDR settings.

Brian Flinn
Expert 1180 points
Other Parts Discussed in Thread: OMAP-L138

I'm trying to find the source file(s) responsible for setting up the
OMAP_L138 external DDR memory timing and setup registers under u-boot.
I'm using a Logic pd Zoom OMAP_L138 evm baseboard with OMAP_L138 SOM

I have
ti-dvsdk_omapl138-evm_4_02_00_06/psp/u-boot-2009.11-psp03.20.00.14

Im looking for the source file(s) that does the setting of bits in registers such as
EMIF3A_SDCR etc.  I.E. everything to set up the external memory controller / interface number 3.

It is not being done in anything involving
u-boot-2009.11-psp03.20.00.14/include/configs/da850evm.h
or
u-boot-2009.11-psp03.20.00.14/board/davinci/common/misc.c
or
u-boot-2009.11-psp03.20.00.14/board/davinci/da8xxevm/da850evm.c

If anyone can help me find the file(s) thanks ?

Brian

  • 0
    TI__Guru 64490 points

    If you are really targeting the DDR interface, it would not be the EMIFA interface.  On the LogicPD board the EMIFA is used for asynchronous memory and not DRAM.  The OMAP-L138 has a dedicated DDR2/mDDR interface which the DRAM is connected to.

    That said, I simply performed a grep on a register name, such as "SDTIM" in the u-boot source directory to determine the initialization code is in the ./cpu/arm926ejs/davinci/lowlevel_init.S file.

    [host] grep -R "SDTIM" *

    board/netta/dsp.c:#define SDTIM (DRAM_REGS_BASE + 0x1C)
    board/netta/dsp.c:      c62_write_word(SDTIM, 1536);
    cpu/arm926ejs/davinci/lowlevel_init.S:  ldr     r6, SDTIM0
    cpu/arm926ejs/davinci/lowlevel_init.S:  ldr     r7, SDTIM0_VAL_162MHz
    cpu/arm926ejs/davinci/lowlevel_init.S:  ldr     r6, SDTIM1
    cpu/arm926ejs/davinci/lowlevel_init.S:  ldr     r7, SDTIM1_VAL_162MHz
    cpu/arm926ejs/davinci/lowlevel_init.S:SDTIM0:
    cpu/arm926ejs/davinci/lowlevel_init.S:SDTIM0_VAL_162MHz:
    cpu/arm926ejs/davinci/lowlevel_init.S:SDTIM1:
    cpu/arm926ejs/davinci/lowlevel_init.S:SDTIM1_VAL_162MHz:
    include/asm-arm/arch-davinci/emif_defs.h:       dv_reg          SDTIMR;