Part Number: TDA4AL-Q1
Hi, TI Expert
As titile description, I try to use CCS debug vision_apps R5 RTOS applications, but get error as below.
Do I miss any thing?
Many Thanks
Gibbs
Console log,
CORTEX_M4F_0: GEL Output: Configuring ATCM for the R5Fs CORTEX_M4F_0: GEL Output: ATCM Configured. CORTEX_M4F_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC. CORTEX_M4F_0: GEL Output: Do not run this GEL from any other CPU on the SoC. CORTEX_M4F_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000]. CORTEX_M4F_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000]. CORTEX_M4F_0: GEL Output: This is consistent with the SoC DV assumptions. CORTEX_M4F_0: GEL Output: R5F Halt bits set. CORTEX_M4F_0: GEL Output: C71X_x DSPs configured for Wait In Reset Mode CORTEX_M4F_0: GEL Output: Debugging disabled. CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Checking LPSC_WKUPMCU2MAIN CORTEX_M4F_0: GEL Output: Power Domain: On CORTEX_M4F_0: GEL Output: Module State: Enable CORTEX_M4F_0: GEL Output: Programming all PLLs. CORTEX_M4F_0: GEL Output: Programming Main PLL 0 (Main PLL) CORTEX_M4F_0: GEL Output: Main PLL 0 (Main PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL) CORTEX_M4F_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 3 (CPSW5X PLL) CORTEX_M4F_0: GEL Output: Main PLL 3 (CPSW5X PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 4 (Audio 0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 4 (Audio 0 PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 5 (Video PLL) CORTEX_M4F_0: GEL Output: Main PLL 5 (Video PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 7 (MSMC PLL) CORTEX_M4F_0: GEL Output: Main PLL 7 (MSMC PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 8 (ARM0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 8 (ARM0 PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL) CORTEX_M4F_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 16 (DSS0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 16 (DSS0 PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 17 (DSS1 PLL) CORTEX_M4F_0: GEL Output: Main PLL 17 (DSS1 PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 19 (DSS3 PLL) CORTEX_M4F_0: GEL Output: Main PLL 19 (DSS3 PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 25 (Vision PLL) CORTEX_M4F_0: GEL Output: Main PLL 25 (Vision PLL) Set. CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL) CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set. CORTEX_M4F_0: GEL Output: Programming MCU PLL 0 (MCU PLL) CORTEX_M4F_0: GEL Output: MCU PLL 0 (MCU PLL) Set. CORTEX_M4F_0: GEL Output: Programming MCU PLL 1 (MCU Peripheral PLL) CORTEX_M4F_0: GEL Output: MCU PLL 1 (MCU PLL) Set. CORTEX_M4F_0: GEL Output: Programming MCU PLL 2 (MCU CPSW PLL) CORTEX_M4F_0: GEL Output: MCU PLL 2 (MCU PLL) Set. CORTEX_M4F_0: GEL Output: All PLLs programmed. CORTEX_M4F_0: GEL Output: Powering up all PSC power domains in progress... CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_ALWAYSON CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_DMSC CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_DEBUG2DMSC CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_GPIO CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN2WKUPMCU CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_TEST CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_DEBUG CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_MCAN_0 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_MCAN_1 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_OSPI_0 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_OSPI_1 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_HYPERBUS CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_I3C_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_ADC_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_ADC_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_WKUP_SPARE_0 (HSM) CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_R5_0 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_R5_1 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MCU_PULSAR_PBIST_0 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_ALWAYSON CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_TEST CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_PBIST CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_AUDIO CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_ATL CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MLB CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MOTOR CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_MISCIO CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_GPMC CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_VPFE CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_VPE CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_1 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_DEBUG CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_CFG_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_EMIF_DATA_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_SPARE_2 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC4B_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC4B_1 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MMC8B_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_SAUL CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PER_I3C CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_SERDES_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_2 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_3 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_4 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_5 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_6 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_7 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_8 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_9 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_10 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_11 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_12 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_MAIN_MCANSS_13 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_DSS_PBIST CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_DSS CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_TX_DPHY_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_DSI CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_EDP_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_CSITX_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_PHY_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_PHY_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_CSIRX_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_CSITX_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_TX_DPHY_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_DSI_1_PBIST CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PCIe_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_0 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_1 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_2 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_DMTIMER_3 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powered up all Main Timers. CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_USB_2 CORTEX_M4F_0: GEL Output: No change needed. CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_0_PBIST CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_C71X_1_PBIST CORTEX_M4F_0: GEL Output: ERROR: module state NOT changed! CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_CLUSTER_0_PBIST CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_A72_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUCOM CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUPBIST CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_GPUCORE CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_0_PBIST CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_PULSAR_1_PBIST CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_1 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_ENCODE_1_PBIST CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_DMPAC CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_SDE CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_DMPAC_PBIST CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_VPAC_PBIST CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up LPSC_CPSW_2 CORTEX_M4F_0: GEL Output: Power domain and module state changed successfully. CORTEX_M4F_0: GEL Output: Powering up all PSC power domains done! CORTEX_M4F_0: GEL Output: MCU R5F Cluster set to split mode. CORTEX_M4F_0: GEL Output: Main R5F Cluster 0 set to split mode. CORTEX_M4F_0: GEL Output: Main R5F Cluster 1 set to split mode. CORTEX_M4F_0: GEL Output: --->>> ================================================== <<<--- CORTEX_M4F_0: GEL Output: --->>> Set DDR Interelave Configuration: <<<--- CORTEX_M4F_0: GEL Output: --->>> multi DDR config 0 : 0x0x000B0003 <<<--- CORTEX_M4F_0: GEL Output: --->>> multi DDR config 1 : 0x0x00000003 <<<--- CORTEX_M4F_0: GEL Output: --->>> Dual DDR enabled <<<--- CORTEX_M4F_0: GEL Output: --->>> 128B Granule Size <<<--- CORTEX_M4F_0: GEL Output: --->>> ================================================== <<<--- CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is in progress ... <<<--- CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to 20MHz/19.2MHz on silicon (bypass) CORTEX_M4F_0: GEL Output: Set DDR0 PLL to external bypass (20MHz/19.2MHz on SVB/EVM). CORTEX_M4F_0: GEL Output: --->>> DDR0 controller programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 controller programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PI programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PI programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 0 programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 0 programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 1 programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 1 programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 2 programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 2 programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 3 programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Data Slice 3 programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Address slice 0 programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY Address Slice 0 programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR0 PHY programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR PI initialization started... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR Controller initialization started... <<<--- CORTEX_M4F_0: GEL Output: --->>> Waiting for frequency change requests ... <<<--- CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to 20MHz/19.2MHz on silicon (bypass) CORTEX_M4F_0: GEL Output: Set DDR0 PLL to external bypass (20MHz/19.2MHz on SVB/EVM). CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to 20MHz/19.2MHz on silicon (bypass) CORTEX_M4F_0: GEL Output: Set DDR0 PLL to external bypass (20MHz/19.2MHz on SVB/EVM). CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller CORTEX_M4F_0: GEL Output: Setting DDR0 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 12 (DDR0 PLL) CORTEX_M4F_0: GEL Output: Main PLL 12 (DDR0 PLL) Set. CORTEX_M4F_0: GEL Output: --->>> All frequency change requests have completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is DONE! <<<--- CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is in progress ... <<<--- CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to 20MHz/19.2MHz on silicon (bypass) CORTEX_M4F_0: GEL Output: Set DDR1 PLL to external bypass (20MHz/19.2MHz on SVB/EVM). CORTEX_M4F_0: GEL Output: --->>> DDR1 controller programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 controller programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PI programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PI programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 0 programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 0 programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 1 programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 1 programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 2 programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 2 programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 3 programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Data Slice 3 programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Address slice 0 programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY Address Slice 0 programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY programming in progress.. <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR1 PHY programming completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR PI initialization started... <<<--- CORTEX_M4F_0: GEL Output: --->>> DDR Controller initialization started... <<<--- CORTEX_M4F_0: GEL Output: --->>> Waiting for frequency change requests ... <<<--- CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL) CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to 20MHz/19.2MHz on silicon (bypass) CORTEX_M4F_0: GEL Output: Set DDR1 PLL to external bypass (20MHz/19.2MHz on SVB/EVM). CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL) CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 0 received from controller CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to 20MHz/19.2MHz on silicon (bypass) CORTEX_M4F_0: GEL Output: Set DDR1 PLL to external bypass (20MHz/19.2MHz on SVB/EVM). CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL) CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL) CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL) CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL) CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 1 received from controller CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL) CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set. CORTEX_M4F_0: GEL Output: Frequency change request type 2 received from controller CORTEX_M4F_0: GEL Output: Setting DDR1 PLL to produce a clock at 1066MHz. CORTEX_M4F_0: GEL Output: Programming Main PLL 26 (DDR1 PLL) CORTEX_M4F_0: GEL Output: Main PLL 26 (DDR1 PLL) Set. CORTEX_M4F_0: GEL Output: --->>> All frequency change requests have completed... <<<--- CORTEX_M4F_0: GEL Output: --->>> LPDDR4 Initialization is DONE! <<<--- C71X_0: AutoRun: Target not run as the symbol "main" is not defined MAIN_Cortex_R5_0_0: Trouble Writing Memory Block at 0x400000 on Page 0 of Length 0x714c: (Error -1205 @ 0x401000) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 12.6.0.00029) MAIN_Cortex_R5_0_0: File Loader: Verification failed: Target failed to write 0x00400000 MAIN_Cortex_R5_0_0: GEL: File: /home/gibbs/work/tda4s2/ti-processor-sdk-rtos-j721s2-evm-09_01_00_06/vision_apps/out/J721S2/A72/LINUX/debug/vx_app_multi_cam.out: Load failed.
