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AM620-Q1: Clarification on memory mapping of DDR subsystem

Nikita Kadam
Prodigy 40 points
Part Number: AM620-Q1
Other Parts Discussed in Thread: AM620

Hi
I am using AM620 for my project. I want to connect an external DDR for the project. From the TRM(Technical reference Manual)  I understand that I can interface DDR via DDR subsystem (DDR16SS0). I wanted clarification on memory mapping of DDR subsystem. The reason I am asking it is because, I found different address ranges in different sections of the TRM. 
[reference pages: page no. 809, 
                             page no. 37 & 47,
                             page no. 56,65 & 70]

[reference link: AM62x Sitara Processors Technical Reference Manual (Rev. B) (ti.com)]

Thanks in advance

  • 0
    TI__Guru* 81180 points

    page 37 refers to the memory map of the Subsystem and Controller/PHY registers in the DDR subsystem

    pg 43 refers to the first 2GByte of addressable memory space

    pg 47 refers to the next 6GBytes of addressable memory space.  Check table 5-1 in the datasheet to determine which memory types can use the full memory range

    pg 809 reflects the info in pg 43 and pg47

    pg 56, 65 and 70  refers to the memory map of each of the cores in the device.  Note: cores other than the A53 have to use the RAT to address the DDR

    Regards,

    James