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TDA4VM: Question for DDR4 memory check

cheolweon jang
Prodigy 40 points
Part Number: TDA4VM


Hello


Currently, we use a combination of LPDDR4 memory for TDA4VM

As far as I know, the maximum bandwice of LPDDR4 is 17GB/s,
 
But, When using the "appPerfStatsDrStatsPrint"  API supported by TI SDK7.1, the vlaue of PEAKs exceeds the maximum bandwidth(17GB/s).

Looking at the PEAK calculation part, it is as follows, but I would like to ask if it is the right way to measure by adding write and read as shown in the formula below.
printf("DDR: READ BW: AVG = %6d MB/s, PEAK = %6d MB/s\n",
ddr_load->read_bw_avg,
ddr_load->read_bw_peak);
printf("DDR: WRITE BW: AVG = %6d MB/s, PEAK = %6d MB/s\n",
ddr_load->write_bw_avg,
ddr_load->write_bw_peak);
printf("DDR: TOTAL BW: AVG = %6d MB/s, PEAK = %6d MB/s\n",
ddr_load->read_bw_avg+ddr_load->write_bw_avg,
ddr_load->write_bw_peak+ddr_load->read_bw_peak);
Thanks
Best regards
  • 0
    TI__Guru* 87096 points

    Hi,

    SDK 7.1 is a very old release. Could you please do the same test with our latest SDK 9.1 and check if you are still facing this issue?

    Regards,

    Nikhil

  • 0 in reply to Nikhil Dasan
    Prodigy 40 points

    It's a little bit hard to testing SDK 9.1

    because this environment is our custom setting.

    I just want to know the formula is reasonable.

    If the formula is correct, I would like to ask if there may be a problem with the measurement differently depending on the sdk version.

    thanks

    Regards,

    Jang

  • 0 in reply to cheolweon jang
    TI__Guru* 87096 points

    Hi Jang,

    Do you see ddr_load->write_bw_peak  and ddr_load->read_bw_peak individually going above the total bandwidth?

    Or only see it going above when you add both?

    If it is the latter, then the peaks are updated at different intervals. i.e. a read peak and write peak would not have occurred at the same time but could have occurred at different instances. 

    So, you should consider them individually rather than together.

    Regards,

    Nikhil