TDA4VM: Enable CPSW0 Main Domain Ethernet Switch with SGMII Interface in U-Boot

Hi Felix,

As you are using SGMII MAC port 7, you would be using the 4 lane serdes. This serdes is not powered on be default and the probe for this serdes has to be added. Have you done this?

It looks like serdes might be the issue. Can you print out the following registers:

• 0x0505E000
• 0x05050480
• 0x050504C0
• 0x05050500
• 0x05050540
• 0x05050484
• 0x050504C4
• 0x05050504
• 0x05050544
• 0x05050488
• 0x050504C8
• 0x05050508
• 0x05050548
• 0x0505040C
• 0x05050408

If you get a crash while reading the registers, the serdes is not powered on.

Regards,
Tanmay

Hi Tanmay,

thanks for your quick response. I did not get a crash while reading out these registers. This are the results:

=> md 0x505E000 1
0505e000: 000c0000                             ....
=> md 0x5050480 1
05050480: 00000000                             ....
=> md 0x50504c0 1
050504c0: 00000000                             ....
=> md 0x5050500 1
05050500: 00000000                             ....
=> md 0x5050540 1
05050540: 00000000                             ....
=> md 0x5050484 1
05050484: 00000000                             ....
=> md 0x50504c4 1
050504c4: 00000000                             ....
=> md 0x5050504 1
05050504: 00000000                             ....
=> md 0x5050544 1
05050544: 00000000                             ....
=> md 0x5050488 1
05050488: 00000000                             ....
=> md 0x50504c8 1
050504c8: 00000000                             ....
=> md 0x5050508 1
05050508: 00000000                             ....
=> md 0x5050548 1
05050548: 00000000                             ....
=> md 0x505040c 1
0505040c: 00000000                             ....
=> md 0x5050408 1
05050408: 08000000                             ....

serdes 4 device tree node (from k3-j721e-main.dts) looks the following:

	serdes_wiz4: wiz@5050000 {
		compatible = "ti,j721e-wiz-16g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 297 9>;
		assigned-clock-parents = <&k3_clks 297 10>;
		assigned-clock-rates = <19200000>;
		num-lanes = <4>;
		#reset-cells = <1>;
		ranges = <0x5050000 0x0 0x5050000 0x10000>,
			<0xa030a00 0x0 0xa030a00 0x40>;

		wiz4_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll0_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll1_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_refclk_dig: refclk-dig {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_refclk_dig";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_refclk_dig>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz4_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz4_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes4: serdes@5050000 {
			/*
			 * Note: we also map DPTX PHY registers as the Torrent
			 * needs to manage those.
			 */
			compatible = "ti,j721e-serdes-10g";
			reg = <0x5050000 0x10000>,
			      <0xa030a00 0x40>; /* DPTX PHY */
			reg-names = "torrent_phy", "dptx_phy";

			resets = <&serdes_wiz4 0>;
			reset-names = "torrent_reset";
			clocks = <&wiz4_pll0_refclk>;
			clock-names = "refclk";
			#address-cells = <1>;
			#size-cells = <0>;
			
			serdes4_sgmii_link: phy@0 {
				reg = <0>;
				resets = <&serdes_wiz4 1>, <&serdes_wiz4  2>, <&serdes_wiz4 3>, <&serdes_wiz4 4>;
				cdns,phy-type = <PHY_TYPE_SGMII>;
				cdns,num-lanes = <4>;
				#phy-cells = <0>;
			};
		};
	};

I tried to change the "compatible" field to "ti,j721e-wiz-10g", since in TRM this SERDES instance is mentioned as SERDES_10G0. But this results in a crash, when I try to read out register 0x0505E000.

Best regards,

Felix

Update:

Strangely, I am now getting a crash everytime, when I try to read out 0x0505E000. Although I went back to the serdes device tree node I posted in the previous post.

The crash dump looks the following:

=> md 0x505E000 1
"Error" handler, esr 0xbf000000
elr: 00000000808bda68 lr : 00000000808ba13c (reloc)
elr: 00000000fff8fa68 lr : 00000000fff8c13c
x0 : 00000000fde99109 x1 : 00000000fffac8c9
x2 : 00000000fde99020 x3 : 00000000ffffffd0
x4 : 00000000ffffffff x5 : 00000000fde98e98
x6 : 0000000000000030 x7 : 00000000fde99050
x8 : 00000000fff13ed4 x9 : 0000000000000008
x10: 00000000ffffffd8 x11: 0000000000000010
x12: 0000000000000040 x13: 000000000001869f
x14: 00000000fde99470 x15: 0000000000000021
x16: 00000000ffee9268 x17: 0000000000000000
x18: 00000000fdeb1db0 x19: 0000000000000004
x20: 0000000000000004 x21: 0000000000000001
x22: 000000000505e004 x23: 00000000fde99109
x24: 0000000000000000 x25: 00000000fde990b8
x26: 00000000fffac8c9 x27: 0000000000000008
x28: 0000000000000004 x29: 00000000fde98fd0

Code: b9004fff a9430fe2 a9010fe2 a9440fe2 (a9020fe2) 
Resetting CPU ...

resetting ...

Update: 

Reading CPSW_SGMII_STATUS_REG_j gives the following output:

=> md 0x0c000114 1
0c000114: 00000028                             (...
=> md 0x0c000214 1
0c000214: 00000028                             (...
=> md 0x0c000314 1
0c000314: 0000002c                             ,...
=> md 0x0c000414 1
0c000414: 0000002c                             ,...
=> md 0x0c000514 1
0c000514: 00000028                             (...
=> md 0x0c000614 1
0c000614: 00000028                             (...
=> md 0x0c000714 1
0c000714: 00000000                             ....
=> md 0x0c000814 1
0c000814: 0000002a                             *...

So for SGMII on port 7 (0x0c000714), The SERDES PLL is not locked and link is therefore also not up.

Can you show me how to properly initialize serdes4 instance for my use case?

Thanks for your help and best regards,

Felix

Hi TI, 

I would just like to kindly remind you of this question.

Best regards,

Felix

Hi TI,

the following parts were missing in my U-Boot code:

• CONFIG_PHY_CADENCE_TORRENT was not activated in my config
• configure_serdes_torrent() was not called in board_late_init()

With these changes, I am now getting the following U-Boot Log:

U-Boot 2023.04-a72-emmc-develop-g3849cd137b-dirty (Apr 05 2024 - 12:22:32 +0200)

SoC:   J721E SR1.1 GP
Model: Texas Instruments K3 J721E SoC
DRAM:  4 GiB
Core:  116 devices, 34 uclasses, devicetree: separate
Warning: Device tree includes old 'u-boot,dm-' tags: please fix by 2023.07!
Flash: 0 Bytes
MMC:   mmc@4f80000: 0
Loading Environment from MMC... OK
In:    serial@2860000
Out:   serial@2860000
Err:   serial@2860000
am65_cpsw_nuss ethernet@c000000: K3 CPSW: nuss_ver: 0x6BA01901 cpsw_ver: 0x6BA80101 ale_ver: 0x00294104 Ports:3 mdio_freq:1000000
cdns,sierra serdes@5000000: sierra probed
cdns,torrent serdes@5050000: phy ref clock not found
Torrent init failed:-19
Net:   eth1: ethernet@c000000port@5, eth2: ethernet@c000000port@6, eth0: ethernet@c000000port@7
Hit any key to stop autoboot:  0 
=> 

Still, there seems to be some error with Serdes4 instance: cdns,torrent serdes@5050000: phy ref clock not found

The Device Tree for Serdes4 looks the following:

	serdes_wiz4: wiz@5050000 {
		compatible = "ti,am64-wiz-10g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 297 9>;
		assigned-clock-parents = <&k3_clks 297 13>;
		num-lanes = <4>;
		#reset-cells = <1>;
		ranges = <0x5050000 0x0 0x5050000 0x10000>,
			<0xa030a00 0x0 0xa030a00 0x40>;

		wiz4_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll0_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll1_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_refclk_dig: refclk-dig {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_refclk_dig";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_refclk_dig>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz4_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz4_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes4: serdes@5050000 {
			/*
			 * Note: we also map DPTX PHY registers as the Torrent
			 * needs to manage those.
			 */
			compatible = "ti,j721e-serdes-10g";
			reg = <0x5050000 0x10000>,
			      <0xa030a00 0x40>; /* DPTX PHY */
			reg-names = "torrent_phy", "dptx_phy";

			resets = <&serdes_wiz4 0>;
			reset-names = "torrent_reset";
			clocks = <&wiz4_pll0_refclk>;
			clock-names = "refclk";
			#address-cells = <1>;
			#size-cells = <0>;
			serdes4_sgmii_link: phy@0 {
				reg = <0>;
				resets = <&serdes_wiz4 1>, <&serdes_wiz4  2>, <&serdes_wiz4 3>, <&serdes_wiz4 4>;
				cdns,phy-type = <PHY_TYPE_SGMII>;
				cdns,num-lanes = <4>;
				#phy-cells = <0>;
			};
		};
	};

I changed the compatible field to "ti,am64-wiz-10g" and I changed assigned-clock-parents = <&k3_clks 297 13>;

Print out of Serdes4 registers gives the following:

=> md 0x505E000 1
0505e000: 000c0000                             ....
=> md 0x5050480 1
05050480: 30000000                             ...0
=> md 0x50504c0 1
050504c0: 30000000                             ...0
=> md 0x5050500 1
05050500: 30000000                             ...0
=> md 0x5050540 1
05050540: 30000000                             ...0
=> md 0x5050484 1
05050484: 00010002                             ....
=> md 0x50504c4 1
050504c4: 00010002                             ....
=> md 0x5050504 1
05050504: 00010002                             ....
=> md 0x5050544 1
05050544: 00010002                             ....
=> md 0x5050488 1
05050488: 00000000                             ....
=> md 0x50504c8 1
050504c8: 00000000                             ....
=> md 0x5050508 1
05050508: 00000000                             ....
=> md 0x5050548 1
05050548: 00000000                             ....
=> md 0x505040c 1
0505040c: 00000000                             ....
=> md 0x5050408 1
05050408: 98000000                             ....

Reading CPSW_SGMII_STATUS_REG_j gives the following output:

=> md 0x0c000114 1
0c000114: 00000028                             (...
=> md 0x0c000214 1
0c000214: 00000028                             (...
=> md 0x0c000314 1
0c000314: 00000028                             (...
=> md 0x0c000414 1
0c000414: 0000002c                             ,...
=> md 0x0c000514 1
0c000514: 00000000                             ....
=> md 0x0c000614 1
0c000614: 00000000                             ....
=> md 0x0c000714 1
0c000714: 00000000                             ....
=> md 0x0c000814 1
0c000814: 00000028                             (...

Best regards,

Felix

Hi TI,

just a quick reminder regarding this issue.

Best regards,

Felix

Hi Felix,

Sorry for the delay.

Can you make the following changes in your current setup:

1. Make the compatible sting for wiz as : "ti,j721e-wiz-10g"
2. Make the compatible string for serdes as : "ti,j721e-serdes-10g"
3. Remove the DPHY ranges from the serdes node.
4. In the "clocks" property in the serdes node, put "&k3_clks 297 9" instead of "&wiz4_pll0_refclk"

Regards,
Tanmay

Hi Tanmay,

thanks for your response.

I applied all of your suggestions. The Boot log looks now the following: (I added " dev_info(dev, "torrent probed\n");" at the end of cdns_torrent_phy_probe)

U-Boot 2023.04-a72-emmc-develop-g3849cd137b-dirty (Apr 17 2024 - 11:08:19 +0200)

SoC:   J721E SR1.1 GP
Model: Texas Instruments K3 J721E SoC
DRAM:  4 GiB
Core:  116 devices, 34 uclasses, devicetree: separate
Warning: Device tree includes old 'u-boot,dm-' tags: please fix by 2023.07!
Flash: 0 Bytes
MMC:   mmc@4f80000: 0
Loading Environment from MMC... OK
In:    serial@2860000
Out:   serial@2860000
Err:   serial@2860000
am65_cpsw_nuss ethernet@c000000: K3 CPSW: nuss_ver: 0x6BA01901 cpsw_ver: 0x6BA80101 ale_ver: 0x00294104 Ports:3 mdio_freq:1000000
cdns,sierra serdes@5000000: sierra probed
cdns,torrent serdes@5050000: torrent probed
Net:   eth1: ethernet@c000000port@5, eth2: ethernet@c000000port@6, eth0: ethernet@c000000port@7
Hit any key to stop autoboot:  0 
=>

So the previous mentioned error  "phy ref clock not found" seems to be solved. However, I still can not get a valid IP address using dhcp command:

=> mdio list
mdio@f00:
ethernet@c000000port@5:
0 - TI DP83867 <--> ethernet@c000000port@5
1 - TI DP83867 <--> ethernet@c000000port@6
2 - TI DP83867 <--> ethernet@c000000port@7
=> net list 
eth1 : ethernet@c000000port@5 2e:a2:59:4c:cc:4f 
eth2 : ethernet@c000000port@6 6a:7a:c7:02:0a:a4 
eth0 : ethernet@c000000port@7 82:11:18:93:eb:cd active
=> dhcp
k3-navss-ringacc ringacc@3c000000: Ring Accelerator probed rings:1024, gp-rings[440,150] sci-dev-id:211
k3-navss-ringacc ringacc@3c000000: dma-ring-reset-quirk: disabled
am65_cpsw_nuss_port ethernet@c000000port@7: K3 CPSW: rflow_id_base: 16
link up on port 7, speed 1000, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
BOOTP broadcast 8
BOOTP broadcast 9
BOOTP broadcast 10
BOOTP broadcast 11
BOOTP broadcast 12
BOOTP broadcast 13
BOOTP broadcast 14
BOOTP broadcast 15
BOOTP broadcast 16
BOOTP broadcast 17

Retry time exceeded; starting again

Print out of Serdes4 registers gives the following:

=> md 0x505E000 1
0505e000: 000c0000                             ....
=> md 0x5050480 1
05050480: 30000000                             ...0
=> md 0x50504c0 1
050504c0: 30000000                             ...0
=> md 0x5050500 1
05050500: 30000000                             ...0
=> md 0x5050540 1
05050540: 30000000                             ...0
=> md 0x5050484 1
05050484: 00010002                             ....
=> md 0x50504c4 1
050504c4: 00010002                             ....
=> md 0x5050504 1
05050504: 00010002                             ....
=> md 0x5050544 1
05050544: 00010002                             ....
=> md 0x5050488 1
05050488: 00000000                             ....
=> md 0x50504c8 1
050504c8: 00000000                             ....
=> md 0x5050508 1
05050508: 00000000                             ....
=> md 0x5050548 1
05050548: 00000000                             ....
=> md 0x505040c 1
0505040c: 00000000                             ....
=> md 0x5050408 1
05050408: 98000000                             ....

Print out CPSW_SGMII_STATUS_REG_j gives the following:

=> md 0x0c000114 1
0c000114: 00000028                             (...
=> md 0x0c000214 1
0c000214: 00000028                             (...
=> md 0x0c000314 1
0c000314: 00000028                             (...
=> md 0x0c000414 1
0c000414: 0000002c                             ,...
=> md 0x0c000514 1
0c000514: 00000000                             ....
=> md 0x0c000614 1
0c000614: 00000000                             ....
=> md 0x0c000714 1
0c000714: 00000000                             ....
=> md 0x0c000814 1
0c000814: 0000002a                             *...

So for SERDES4 Registers nothing changed and CPSW_SGMII_STATUS_REG_j for port 5,6,7 is also the same.

I think that at least for the LANECTLx SERDES registers, which currently read as 0x3000'0000 there is something not correct and also CPSW_SGMII_STATUS_REG_j  should not be 0x0 for port5, port6 and port7. 

One drawback of the current hardware design is, that I am not able to reset the PHY's via a GPIO on TDA4. Is resetting necessary so that PHY works properly? The Strap Configuration should be correct.

Do you have any other ideas on what is still missing here?

Thanks again for your help.

Best regards,

Felix

Hi Felix,

From the register dump, I can see that the PLL for serdes is not being locked. Its is some issue with the clocking of the serdes itself.

Tanmay Patil said:

In the "clocks" property in the serdes node, put "&k3_clks 297 9" instead of "&wiz4_pll0_refclk"

Can you revert back only the above change and try.

felix_123 said:

Is resetting necessary so that PHY works properly? The Strap Configuration should be correct.

The power-on reset should work with the proper strap configuration. But if you want to use the same phy from linux kernel later, I would think that it would be better to reset it. This question is better asked to the hardware team and I am not very sure regarding this.

Regards,
Tanmay

Hi Tanmay,

I reverted the line you suggested. This is how the serdes4 node looks right now:

	serdes_wiz4: wiz@5050000 {
		compatible = "ti,j721e-wiz-10g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		assigned-clocks = <&k3_clks 297 9>;
		assigned-clock-parents = <&k3_clks 297 13>;
		num-lanes = <4>;
		#reset-cells = <1>;
		ranges = <0x5050000 0x0 0x5050000 0x10000>;

		wiz4_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll0_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_pll1_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_refclk_dig: refclk-dig {
			clocks = <&k3_clks 297 9>, <&cmn_refclk>;
			clock-output-names = "wiz4_refclk_dig";
			#clock-cells = <0>;
			assigned-clocks = <&wiz4_refclk_dig>;
			assigned-clock-parents = <&k3_clks 297 9>;
		};

		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz4_refclk_dig>;
			#clock-cells = <0>;
		};

		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
			clocks = <&wiz4_pll1_refclk>;
			#clock-cells = <0>;
		};

		serdes4: serdes@5050000 {
			/*
			 * Note: we also map DPTX PHY registers as the Torrent
			 * needs to manage those.
			 */
			compatible = "ti,j721e-serdes-10g";
			reg = <0x5050000 0x10000>;
			reg-names = "torrent_phy";

			resets = <&serdes_wiz4 0>;
			reset-names = "torrent_reset";
			clocks = <&wiz4_pll0_refclk>;
			clock-names = "refclk";
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

processor-board-device treee contains the following ethernet related nodes:

&main_pmx0 {
	mymdio1_pins_default: mymdio1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
		>;
	};
	
};

&serdes4 {
	serdes4_sgmii_link: phy@0 {
		reg = <0>;
		resets = <&serdes_wiz4 1>, <&serdes_wiz4  2>, <&serdes_wiz4 3>, <&serdes_wiz4 4>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		cdns,num-lanes = <4>;
		#phy-cells = <0>;
	};
};

&main_cpsw0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mymdio1_pins_default>;
};

&main_cpsw0_mdio {

	//reset-gpios = <&wkup_gpio1 50 GPIO_ACTIVE_LOW>;
	//reset-port-delay-us = <120000>;
	
	cpsw9g_phy0: ethernet-phy@0 {
		reg = <0>;
		compatible = "ti,dp83867";
	};
	cpsw9g_phy1: ethernet-phy@1 {
		reg = <1>;
		compatible = "ti,dp83867";
	};
	cpsw9g_phy2: ethernet-phy@2 {
		reg = <2>;
		compatible = "ti,dp83867";
	};
};


&main_cpsw0_port5 {
	status = "okay";
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&main_phy_gmii_sel 5>, <&serdes4_sgmii_link>;
	phy-names = "mac", "serdes";
    phy-handle = <&cpsw9g_phy0>;
};

&main_cpsw0_port6 {
	status = "okay";
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&main_phy_gmii_sel 6>, <&serdes4_sgmii_link>;
    phy-names = "mac", "serdes";
    phy-handle = <&cpsw9g_phy1>;
};

&main_cpsw0_port7 {
	status = "okay";
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&main_phy_gmii_sel 7>, <&serdes4_sgmii_link>;
    phy-names = "mac", "serdes";
    phy-handle = <&cpsw9g_phy2>;
};

The bootlog and serdes registers show now the following:

U-Boot 2023.04-a72-emmc-develop-g3849cd137b-dirty (Apr 18 2024 - 08:31:22 +0200)

SoC:   J721E SR1.1 GP
Model: Texas Instruments K3 J721E SoC
DRAM:  4 GiB
Core:  116 devices, 34 uclasses, devicetree: separate
Warning: Device tree includes old 'u-boot,dm-' tags: please fix by 2023.07!
Flash: 0 Bytes
MMC:   mmc@4f80000: 0
Loading Environment from MMC... OK
In:    serial@2860000
Out:   serial@2860000
Err:   serial@2860000
am65_cpsw_nuss ethernet@c000000: K3 CPSW: nuss_ver: 0x6BA01901 cpsw_ver: 0x6BA80101 ale_ver: 0x00294104 Ports:3 mdio_freq:1000000
cdns,sierra serdes@5000000: sierra probed
cdns,torrent serdes@5050000: Failed to prepare ref clock
Torrent init failed:-38
Net:   eth1: ethernet@c000000port@5, eth2: ethernet@c000000port@6, eth0: ethernet@c000000port@7
Hit any key to stop autoboot:  0 
=> md 0x505E000 1
0505e000: 000c0000                             ....
=> md 0x5050480 1
05050480: 30000000                             ...0
=> md 0x50504c0 1
050504c0: 30000000                             ...0
=> md 0x5050500 1
05050500: 30000000                             ...0
=> md 0x5050540 1
05050540: 30000000                             ...0
=> md 0x5050484 1
05050484: 00010002                             ....
=> md 0x50504c4 1
050504c4: 00010002                             ....
=> md 0x5050504 1
05050504: 00010002                             ....
=> md 0x5050544 1
05050544: 00010002                             ....
=> md 0x5050488 1
05050488: 00000000                             ....
=> md 0x50504c8 1
050504c8: 00000000                             ....
=> md 0x5050508 1
05050508: 00000000                             ....
=> md 0x5050548 1
05050548: 00000000                             ....
=> md 0x505040c 1
0505040c: 10000000                             ....
=> md 0x5050408 1
05050408: 98000000                             ....

So Torrent init fails now again, but with a different error code. Serdes registers are the same except 0x505040c (SERDES_RST).

Best regards,

Felix

Just one additional information: I am using U-Boot from PSDK Linux v09.01. The patches I mentioned in my initial question were based on PSDK Linux 08.02. Maybe there is some conflict here?

My current phy-j721e-wiz.c looks the following:

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
 * Jean-Jacques Hiblot <jjhiblot@ti.com>
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <asm/gpio.h>
#include <dm/lists.h>
#include <dm/device-internal.h>
#include <regmap.h>
#include <reset-uclass.h>
#include <dt-bindings/phy/phy.h>

#include <dt-bindings/phy/phy-ti.h>

#define WIZ_MAX_INPUT_CLOCKS	4
/* To include mux clocks, divider clocks and gate clocks */
#define WIZ_MAX_OUTPUT_CLOCKS	32

#define WIZ_MAX_LANES		4
#define WIZ_MUX_NUM_CLOCKS	3
#define WIZ_DIV_NUM_CLOCKS_16G	2
#define WIZ_DIV_NUM_CLOCKS_10G	1

#define WIZ_SERDES_CTRL		0x404
#define WIZ_SERDES_TOP_CTRL	0x408
#define WIZ_SERDES_RST		0x40c
#define WIZ_SERDES_TYPEC	0x410
#define WIZ_LANECTL(n)		(0x480 + (0x40 * (n)))
#define WIZ_LANEDIV(n)		(0x484 + (0x40 * (n)))

#define WIZ_MAX_LANES		4
#define WIZ_MUX_NUM_CLOCKS	3
#define WIZ_DIV_NUM_CLOCKS_16G	2
#define WIZ_DIV_NUM_CLOCKS_10G	1

#define WIZ_SERDES_TYPEC_LN10_SWAP	BIT(30)
#define WIZ_SERDES_TYPEC_LN23_SWAP	BIT(31)

enum wiz_lane_standard_mode {
	LANE_MODE_GEN1,
	LANE_MODE_GEN2,
	LANE_MODE_GEN3,
	LANE_MODE_GEN4,
};

enum wiz_refclk_mux_sel {
	PLL0_REFCLK,
	PLL1_REFCLK,
	REFCLK_DIG,
};

enum wiz_refclk_div_sel {
	CMN_REFCLK,
	CMN_REFCLK1,
};

enum wiz_clock_input {
	WIZ_CORE_REFCLK,
	WIZ_EXT_REFCLK,
	WIZ_CORE_REFCLK1,
	WIZ_EXT_REFCLK1,
};

/*
 * List of master lanes used for lane swapping
 */
enum wiz_typec_master_lane {
	LANE0 = 0,
	LANE2 = 2,
};

static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
static const struct reg_field pll1_refclk_mux_sel =
					REG_FIELD(WIZ_SERDES_RST, 29, 29);
static const struct reg_field pll1_refclk_mux_sel_2 =
					REG_FIELD(WIZ_SERDES_RST, 22, 23);
static const struct reg_field pll0_refclk_mux_sel =
					REG_FIELD(WIZ_SERDES_RST, 28, 28);
static const struct reg_field pll0_refclk_mux_sel_2 =
					REG_FIELD(WIZ_SERDES_RST, 28, 29);
static const struct reg_field refclk_dig_sel_16g =
					REG_FIELD(WIZ_SERDES_RST, 24, 25);
static const struct reg_field refclk_dig_sel_10g =
					REG_FIELD(WIZ_SERDES_RST, 24, 24);
static const struct reg_field pma_cmn_refclk_int_mode =
					REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
static const struct reg_field pma_cmn_refclk1_int_mode =
					REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21);
static const struct reg_field pma_cmn_refclk_mode =
					REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
static const struct reg_field pma_cmn_refclk_dig_div =
					REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
static const struct reg_field pma_cmn_refclk1_dig_div =
					REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);

static const struct reg_field p_enable[WIZ_MAX_LANES] = {
	REG_FIELD(WIZ_LANECTL(0), 30, 31),
	REG_FIELD(WIZ_LANECTL(1), 30, 31),
	REG_FIELD(WIZ_LANECTL(2), 30, 31),
	REG_FIELD(WIZ_LANECTL(3), 30, 31),
};

enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };

static const struct reg_field p_align[WIZ_MAX_LANES] = {
	REG_FIELD(WIZ_LANECTL(0), 29, 29),
	REG_FIELD(WIZ_LANECTL(1), 29, 29),
	REG_FIELD(WIZ_LANECTL(2), 29, 29),
	REG_FIELD(WIZ_LANECTL(3), 29, 29),
};

static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
	REG_FIELD(WIZ_LANECTL(0), 28, 28),
	REG_FIELD(WIZ_LANECTL(1), 28, 28),
	REG_FIELD(WIZ_LANECTL(2), 28, 28),
	REG_FIELD(WIZ_LANECTL(3), 28, 28),
};

static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
	REG_FIELD(WIZ_LANECTL(0), 24, 25),
	REG_FIELD(WIZ_LANECTL(1), 24, 25),
	REG_FIELD(WIZ_LANECTL(2), 24, 25),
	REG_FIELD(WIZ_LANECTL(3), 24, 25),
};

static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
	REG_FIELD(WIZ_LANECTL(0), 22, 23),
	REG_FIELD(WIZ_LANECTL(1), 22, 23),
	REG_FIELD(WIZ_LANECTL(2), 22, 23),
	REG_FIELD(WIZ_LANECTL(3), 22, 23),
};

static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
	REG_FIELD(WIZ_LANEDIV(0), 16, 22),
	REG_FIELD(WIZ_LANEDIV(1), 16, 22),
	REG_FIELD(WIZ_LANEDIV(2), 16, 22),
	REG_FIELD(WIZ_LANEDIV(3), 16, 22),
};

static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
	REG_FIELD(WIZ_LANEDIV(0), 0, 8),
	REG_FIELD(WIZ_LANEDIV(1), 0, 8),
	REG_FIELD(WIZ_LANEDIV(2), 0, 8),
	REG_FIELD(WIZ_LANEDIV(3), 0, 8),
};

struct wiz_clk_mux_sel {
	enum wiz_refclk_mux_sel mux_sel;
	u32			table[WIZ_MAX_INPUT_CLOCKS];
	const char		*node_name;
	u32			num_parents;
	u32			parents[WIZ_MAX_INPUT_CLOCKS];
};

struct wiz_clk_div_sel {
	enum wiz_refclk_div_sel div_sel;
	const char		*node_name;
};

static struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
	{
		/*
		 * Mux value to be configured for each of the input clocks
		 * in the order populated in device tree
		 */
		.num_parents = 2,
		.parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
		.mux_sel = PLL0_REFCLK,
		.table = { 1, 0 },
		.node_name = "pll0-refclk",
	},
	{
		.num_parents = 2,
		.parents = { WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK1 },
		.mux_sel = PLL1_REFCLK,
		.table = { 1, 0 },
		.node_name = "pll1-refclk",
	},
	{
		.num_parents = 4,
		.parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK, WIZ_EXT_REFCLK1 },
		.mux_sel = REFCLK_DIG,
		.table = { 1, 3, 0, 2 },
		.node_name = "refclk-dig",
	},
};

static struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
	{
		/*
		 * Mux value to be configured for each of the input clocks
		 * in the order populated in device tree
		 */
		.num_parents = 2,
		.parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
		.mux_sel = PLL0_REFCLK,
		.table = { 1, 0 },
		.node_name = "pll0-refclk",
	},
	{
		.num_parents = 2,
		.parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
		.mux_sel = PLL1_REFCLK,
		.table = { 1, 0 },
		.node_name = "pll1-refclk",
	},
	{
		.num_parents = 2,
		.parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
		.mux_sel = REFCLK_DIG,
		.table = { 1, 0 },
		.node_name = "refclk-dig",
	},
};

static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = {
	{
		.num_parents = 3,
		.parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
		.table = { 2, 3, 0 },
		.node_name = "pll0-refclk",
	},
	{
		.num_parents = 3,
		.parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
		.table = { 2, 3, 0 },
		.node_name = "pll1-refclk",
	},
	{
		.num_parents = 3,
		.parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
		.table = { 2, 3, 0 },
		.node_name = "refclk-dig",
	},
};

static struct wiz_clk_div_sel clk_div_sel[] = {
	{
		.div_sel = CMN_REFCLK,
		.node_name = "cmn-refclk-dig-div",
	},
	{
		.div_sel = CMN_REFCLK1,
		.node_name = "cmn-refclk1-dig-div",
	},
};

enum wiz_type {
	J721E_WIZ_16G,
	J721E_WIZ_10G,
	AM64_WIZ_10G,
	J784S4_WIZ_10G,
	J721S2_WIZ_10G,
};

struct wiz_data {
	enum wiz_type type;
	const struct reg_field *pll0_refclk_mux_sel;
	const struct reg_field *pll1_refclk_mux_sel;
	const struct reg_field *refclk_dig_sel;
	const struct reg_field *pma_cmn_refclk1_dig_div;
	const struct reg_field *pma_cmn_refclk1_int_mode;
	const struct wiz_clk_mux_sel *clk_mux_sel;
	unsigned int clk_div_sel_num;
};

static const struct wiz_data j721e_16g_data = {
	.type = J721E_WIZ_16G,
	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
	.refclk_dig_sel = &refclk_dig_sel_16g,
	.pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
	.clk_mux_sel = clk_mux_sel_16g,
	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G,
};

static const struct wiz_data j721e_10g_data = {
	.type = J721E_WIZ_10G,
	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
	.refclk_dig_sel = &refclk_dig_sel_10g,
	.clk_mux_sel = clk_mux_sel_10g,
	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};

static struct wiz_data am64_10g_data = {
	.type = AM64_WIZ_10G,
	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
	.refclk_dig_sel = &refclk_dig_sel_10g,
	.clk_mux_sel = clk_mux_sel_10g,
	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};

static struct wiz_data j784s4_wiz_10g = {
	.type = J784S4_WIZ_10G,
	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2,
	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2,
	.refclk_dig_sel = &refclk_dig_sel_16g,
	.pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode,
	.clk_mux_sel = clk_mux_sel_10g_2_refclk,
	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};

static struct wiz_data j721s2_10g_data = {
	.type = J721S2_WIZ_10G,
	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
	.refclk_dig_sel = &refclk_dig_sel_10g,
	.clk_mux_sel = clk_mux_sel_10g,
	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};

#define WIZ_TYPEC_DIR_DEBOUNCE_MIN	100	/* ms */
#define WIZ_TYPEC_DIR_DEBOUNCE_MAX	1000

struct wiz {
	struct regmap		*regmap;
	enum wiz_type		type;
	struct wiz_clk_mux_sel	*clk_mux_sel;
	struct wiz_clk_div_sel	*clk_div_sel;
	unsigned int		clk_div_sel_num;
	struct regmap_field	*por_en;
	struct regmap_field	*phy_reset_n;
	struct regmap_field	*phy_en_refclk;
	struct regmap_field	*p_enable[WIZ_MAX_LANES];
	struct regmap_field	*p_align[WIZ_MAX_LANES];
	struct regmap_field	*p_raw_auto_start[WIZ_MAX_LANES];
	struct regmap_field	*p_standard_mode[WIZ_MAX_LANES];
	struct regmap_field	*p_mac_div_sel0[WIZ_MAX_LANES];
	struct regmap_field	*p_mac_div_sel1[WIZ_MAX_LANES];
	struct regmap_field	*p0_fullrt_div[WIZ_MAX_LANES];
	struct regmap_field	*pma_cmn_refclk_int_mode;
	struct regmap_field	*pma_cmn_refclk1_int_mode;
	struct regmap_field	*pma_cmn_refclk_mode;
	struct regmap_field	*pma_cmn_refclk_dig_div;
	struct regmap_field	*pma_cmn_refclk1_dig_div;
	struct regmap_field	*div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
	struct regmap_field	*mux_sel_field[WIZ_MUX_NUM_CLOCKS];

	struct udevice		*dev;
	u32			num_lanes;
	struct gpio_desc	*gpio_typec_dir;
	u32			lane_phy_type[WIZ_MAX_LANES];
	u32			master_lane_num[WIZ_MAX_LANES];
	struct clk		*input_clks[WIZ_MAX_INPUT_CLOCKS];
	unsigned int		id;
	const struct wiz_data	*data;
};

struct wiz_div_clk {
	struct clk parent_clk;
	struct wiz *wiz;
};

struct wiz_mux_clk {
	struct clk parent_clks[4];
	struct wiz *wiz;
};

struct wiz_clk {
	struct wiz *wiz;
};

struct wiz_reset {
	struct wiz *wiz;
};

static ulong wiz_div_clk_get_rate(struct clk *clk)
{
	struct udevice *dev = clk->dev;
	struct wiz_div_clk *priv = dev_get_priv(dev);
	struct wiz_clk_div_sel *data = dev_get_plat(dev);
	struct wiz *wiz = priv->wiz;
	ulong parent_rate = clk_get_rate(&priv->parent_clk);
	u32 val;

	regmap_field_read(wiz->div_sel_field[data->div_sel], &val);

	return parent_rate >> val;
}

static ulong wiz_div_clk_set_rate(struct clk *clk, ulong rate)
{
	struct udevice *dev = clk->dev;
	struct wiz_div_clk *priv = dev_get_priv(dev);
	struct wiz_clk_div_sel *data = dev_get_plat(dev);
	struct wiz *wiz = priv->wiz;
	ulong parent_rate = clk_get_rate(&priv->parent_clk);
	u32 div = parent_rate / rate;

	div = __ffs(div);
	regmap_field_write(wiz->div_sel_field[data->div_sel], div);

	return parent_rate >> div;
}

const struct clk_ops wiz_div_clk_ops = {
	.get_rate = wiz_div_clk_get_rate,
	.set_rate = wiz_div_clk_set_rate,
};

int wiz_div_clk_probe(struct udevice *dev)
{
	struct wiz_div_clk *priv = dev_get_priv(dev);
	struct clk parent_clk;
	int rc;

	rc = clk_get_by_index(dev, 0, &parent_clk);
	if (rc) {
		dev_err(dev, "unable to get parent clock. ret %d\n", rc);
		return rc;
	}
	priv->parent_clk = parent_clk;
	priv->wiz = dev_get_priv(dev->parent);
	return 0;
}

U_BOOT_DRIVER(wiz_div_clk) = {
	.name		= "wiz_div_clk",
	.id		= UCLASS_CLK,
	.priv_auto	= sizeof(struct wiz_div_clk),
	.ops		= &wiz_div_clk_ops,
	.probe		= wiz_div_clk_probe,
};

static int wiz_clk_mux_set_parent(struct clk *clk,  struct clk *parent)
{
	struct udevice *dev = clk->dev;
	struct wiz_mux_clk *priv = dev_get_priv(dev);
	struct wiz_clk_mux_sel *data = dev_get_plat(dev);
	struct wiz *wiz = priv->wiz;
	int i;

	for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++)
		if (parent->dev == priv->parent_clks[i].dev)
			break;

	if (i == ARRAY_SIZE(priv->parent_clks))
		return -EINVAL;

	regmap_field_write(wiz->mux_sel_field[data->mux_sel], data->table[i]);
	return 0;
}

static int wiz_clk_xlate(struct clk *clk, struct ofnode_phandle_args *args)
{
	struct udevice *dev = clk->dev;
	struct wiz_mux_clk *priv = dev_get_priv(dev);
	struct wiz *wiz = priv->wiz;

	clk->id = wiz->id;

	return 0;
}

static const struct clk_ops wiz_clk_mux_ops = {
	.set_parent = wiz_clk_mux_set_parent,
	.of_xlate = wiz_clk_xlate,
};

int wiz_mux_clk_probe(struct udevice *dev)
{
	struct wiz_mux_clk *priv = dev_get_priv(dev);
	int rc;
	int i;

	for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
		rc = clk_get_by_index(dev, i, &priv->parent_clks[i]);
		if (rc)
			priv->parent_clks[i].dev = NULL;
	}
	priv->wiz = dev_get_priv(dev->parent);
	return 0;
}

U_BOOT_DRIVER(wiz_mux_clk) = {
	.name		= "wiz_mux_clk",
	.id		= UCLASS_CLK,
	.priv_auto	= sizeof(struct wiz_mux_clk),
	.ops		= &wiz_clk_mux_ops,
	.probe		= wiz_mux_clk_probe,
};

static int wiz_clk_set_parent(struct clk *clk,  struct clk *parent)
{
	struct udevice *dev = clk->dev;
	struct wiz_clk *priv = dev_get_priv(dev);
	const struct wiz_clk_mux_sel *mux_sel;
	struct wiz *wiz = priv->wiz;
	int num_parents;
	int i, j, id;

	id = clk->id >> 10;

	/* set_parent is applicable only for MUX clocks */
	if (id > TI_WIZ_REFCLK_DIG)
		return 0;

	for (i = 0; i < WIZ_MAX_INPUT_CLOCKS; i++)
		if (wiz->input_clks[i]->dev == parent->dev)
			break;

	if (i == WIZ_MAX_INPUT_CLOCKS)
		return -EINVAL;

	mux_sel = &wiz->clk_mux_sel[id];
	num_parents = mux_sel->num_parents;
	for (j = 0; j < num_parents; j++)
		if (mux_sel->parents[j] == i)
			break;

	if (j == num_parents)
		return -EINVAL;

	regmap_field_write(wiz->mux_sel_field[id], mux_sel->table[j]);

	return 0;
}

static int wiz_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
{
	struct udevice *dev = clk->dev;
	struct wiz_clk *priv = dev_get_priv(dev);
	struct wiz *wiz = priv->wiz;

	clk->id = args->args[0] << 10 | wiz->id;

	return 0;
}

static const struct clk_ops wiz_clk_ops = {
	.set_parent = wiz_clk_set_parent,
	.of_xlate = wiz_clk_of_xlate,
};

int wiz_clk_probe(struct udevice *dev)
{
	struct wiz_clk *priv = dev_get_priv(dev);

	priv->wiz = dev_get_priv(dev->parent);

	return 0;
}

U_BOOT_DRIVER(wiz_clk) = {
	.name		= "wiz_clk",
	.id		= UCLASS_CLK,
	.priv_auto	= sizeof(struct wiz_clk),
	.ops		= &wiz_clk_ops,
	.probe		= wiz_clk_probe,
};

static int wiz_reset_request(struct reset_ctl *reset_ctl)
{
	return 0;
}

static int wiz_reset_free(struct reset_ctl *reset_ctl)
{
	return 0;
}

static int wiz_reset_assert(struct reset_ctl *reset_ctl)
{
	struct wiz_reset *priv = dev_get_priv(reset_ctl->dev);
	struct wiz *wiz = priv->wiz;
	int ret;
	int id = reset_ctl->id;

	if (id == 0) {
		ret = regmap_field_write(wiz->phy_reset_n, false);
		return ret;
	}

	ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
	return ret;
}

static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
{
	switch (wiz->type) {
	case AM64_WIZ_10G:
		if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
		else if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
		break;
	case J721E_WIZ_10G:
	case J784S4_WIZ_10G:
		if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
		break;
	default:
		break;
	}
	return 0;
}

static int wiz_reset_deassert(struct reset_ctl *reset_ctl)
{
	struct wiz_reset *priv = dev_get_priv(reset_ctl->dev);
	struct wiz *wiz = priv->wiz;
	int ret;
	int id = reset_ctl->id;

	ret = wiz_phy_fullrt_div(wiz, id - 1);
	if (ret)
		return ret;

	/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
	if (id == 0) {
		if (wiz->gpio_typec_dir) {
			if (dm_gpio_get_value(wiz->gpio_typec_dir)) {
				regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
						WIZ_SERDES_TYPEC_LN10_SWAP,
						WIZ_SERDES_TYPEC_LN10_SWAP);
			} else {
				regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
						WIZ_SERDES_TYPEC_LN10_SWAP, 0);
			}
		}
	} else {
		/* if no typec-dir gpio was specified and PHY type is
		 * USB3 with master lane number is '0', set LN10 SWAP
		 * bit to '1'
		 */
		u32 num_lanes = wiz->num_lanes;
		int i;

		for (i = 0; i < num_lanes; i++) {
			if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
				switch (wiz->master_lane_num[i]) {
				case LANE0:
					regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
							WIZ_SERDES_TYPEC_LN10_SWAP,
							WIZ_SERDES_TYPEC_LN10_SWAP);
					break;
				case LANE2:
					 regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
							WIZ_SERDES_TYPEC_LN23_SWAP,
							WIZ_SERDES_TYPEC_LN23_SWAP);
					break;
				default:
					break;
				}
			}
		}
	}

	if (id == 0) {
		ret = regmap_field_write(wiz->phy_reset_n, true);
		return ret;
	}

	if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
	else
		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);

	return ret;
}

static struct reset_ops wiz_reset_ops = {
	.request = wiz_reset_request,
	.rfree = wiz_reset_free,
	.rst_assert = wiz_reset_assert,
	.rst_deassert = wiz_reset_deassert,
};

int wiz_reset_probe(struct udevice *dev)
{
	struct wiz_reset *priv = dev_get_priv(dev);

	priv->wiz = dev_get_priv(dev->parent);

	return 0;
}

U_BOOT_DRIVER(wiz_reset) = {
	.name = "wiz-reset",
	.id = UCLASS_RESET,
	.probe = wiz_reset_probe,
	.ops = &wiz_reset_ops,
	.flags = DM_FLAG_LEAVE_PD_ON,
};

static int wiz_reset(struct wiz *wiz)
{
	int ret;

	ret = regmap_field_write(wiz->por_en, 0x1);
	if (ret)
		return ret;

	mdelay(1);

	ret = regmap_field_write(wiz->por_en, 0x0);
	if (ret)
		return ret;

	return 0;
}

static int wiz_p_mac_div_sel(struct wiz *wiz)
{
	u32 num_lanes = wiz->num_lanes;
	int ret;
	int i;

	for (i = 0; i < num_lanes; i++) {
		if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||
		    wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
			ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
			if (ret)
				return ret;

			ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);
			if (ret)
				return ret;
		}
	}

	return 0;
}

static int wiz_mode_select(struct wiz *wiz)
{
	u32 num_lanes = wiz->num_lanes;
	int ret;
	int i;

	for (i = 0; i < num_lanes; i++) {
		if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
			ret = regmap_field_write(wiz->p_standard_mode[i],
						 LANE_MODE_GEN2);
			if (ret)
				return ret;
		}
	}

	return 0;
}

static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
{
	u32 num_lanes = wiz->num_lanes;
	int i;
	int ret;

	for (i = 0; i < num_lanes; i++) {
		ret = regmap_field_write(wiz->p_align[i], enable);
		if (ret)
			return ret;

		ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
		if (ret)
			return ret;
	}

	return 0;
}

static int wiz_init(struct wiz *wiz)
{
	struct udevice *dev = wiz->dev;
	int ret;

	ret = wiz_reset(wiz);
	if (ret) {
		dev_err(dev, "WIZ reset failed\n");
		return ret;
	}

	ret = wiz_mode_select(wiz);
	if (ret) {
		dev_err(dev, "WIZ mode select failed\n");
		return ret;
	}

	ret = wiz_p_mac_div_sel(wiz);
	if (ret) {
		dev_err(dev, "Configuring P0 MAC DIV SEL failed\n");
		return ret;
	}

	ret = wiz_init_raw_interface(wiz, true);
	if (ret) {
		dev_err(dev, "WIZ interface initialization failed\n");
		return ret;
	}

	return 0;
}

static int wiz_regfield_init(struct wiz *wiz)
{
	struct regmap *regmap = wiz->regmap;
	int num_lanes = wiz->num_lanes;
	struct udevice *dev = wiz->dev;
	const struct wiz_data *data = wiz->data;
	int i;

	wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
	if (IS_ERR(wiz->por_en)) {
		dev_err(dev, "POR_EN reg field init failed\n");
		return PTR_ERR(wiz->por_en);
	}

	wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
						   phy_reset_n);
	if (IS_ERR(wiz->phy_reset_n)) {
		dev_err(dev, "PHY_RESET_N reg field init failed\n");
		return PTR_ERR(wiz->phy_reset_n);
	}

	wiz->pma_cmn_refclk_int_mode =
		devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
	if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
		dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
		return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
	}

	if (data->pma_cmn_refclk1_int_mode) {
		wiz->pma_cmn_refclk1_int_mode =
			devm_regmap_field_alloc(dev, regmap, *data->pma_cmn_refclk1_int_mode);
		if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
			dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n");
			return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);
		}
	}

	wiz->pma_cmn_refclk_mode =
		devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
	if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
		dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
		return PTR_ERR(wiz->pma_cmn_refclk_mode);
	}

	wiz->div_sel_field[CMN_REFCLK] =
		devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div);
	if (IS_ERR(wiz->div_sel_field[CMN_REFCLK])) {
		dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
		return PTR_ERR(wiz->div_sel_field[CMN_REFCLK]);
	}

	if (data->pma_cmn_refclk1_dig_div) {
		wiz->div_sel_field[CMN_REFCLK1] =
			devm_regmap_field_alloc(dev, regmap, *data->pma_cmn_refclk1_dig_div);
		if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1])) {
			dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
			return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1]);
		}
	}

	wiz->mux_sel_field[PLL0_REFCLK] =
		devm_regmap_field_alloc(dev, regmap, *data->pll0_refclk_mux_sel);
	if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
		dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
		return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
	}

	wiz->mux_sel_field[PLL1_REFCLK] =
		devm_regmap_field_alloc(dev, regmap, *data->pll1_refclk_mux_sel);
	if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
		dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
		return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
	}

	wiz->mux_sel_field[REFCLK_DIG] =
		devm_regmap_field_alloc(dev, regmap, *data->refclk_dig_sel);
	if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
		dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
		return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
	}

	for (i = 0; i < num_lanes; i++) {
		wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
							   p_enable[i]);
		if (IS_ERR(wiz->p_enable[i])) {
			dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
			return PTR_ERR(wiz->p_enable[i]);
		}

		wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
							  p_align[i]);
		if (IS_ERR(wiz->p_align[i])) {
			dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
			return PTR_ERR(wiz->p_align[i]);
		}

		wiz->p_raw_auto_start[i] =
		  devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
		if (IS_ERR(wiz->p_raw_auto_start[i])) {
			dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
				i);
			return PTR_ERR(wiz->p_raw_auto_start[i]);
		}

		wiz->p_standard_mode[i] =
		  devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
		if (IS_ERR(wiz->p_standard_mode[i])) {
			dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
				i);
			return PTR_ERR(wiz->p_standard_mode[i]);
		}

		wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
		if (IS_ERR(wiz->p0_fullrt_div[i])) {
			dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
			return PTR_ERR(wiz->p0_fullrt_div[i]);
		}

		wiz->p_mac_div_sel0[i] =
		  devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
		if (IS_ERR(wiz->p_mac_div_sel0[i])) {
			dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n",
				i);
			return PTR_ERR(wiz->p_mac_div_sel0[i]);
		}

		wiz->p_mac_div_sel1[i] =
		  devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]);
		if (IS_ERR(wiz->p_mac_div_sel1[i])) {
			dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n",
				i);
			return PTR_ERR(wiz->p_mac_div_sel1[i]);
		}
	}

	return 0;
}

static int wiz_clock_init(struct wiz *wiz)
{
	struct udevice *dev = wiz->dev;
	unsigned long rate;
	struct clk *clk;
	int ret;

	clk = devm_clk_get(dev, "core_ref_clk");
	if (IS_ERR(clk)) {
		dev_err(dev, "core_ref_clk clock not found\n");
		ret = PTR_ERR(clk);
		return ret;
	}
	wiz->input_clks[WIZ_CORE_REFCLK] = clk;

	rate = clk_get_rate(clk);
	if (rate >= 100000000)
		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
	else
		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);

	if (wiz->data->pma_cmn_refclk1_int_mode) {
		clk = devm_clk_get(dev, "core_ref1_clk");
		if (IS_ERR(clk)) {
			dev_err(dev, "core_ref1_clk clock not found\n");
			ret = PTR_ERR(clk);
			return ret;
		}
		wiz->input_clks[WIZ_CORE_REFCLK1] = clk;

		rate = clk_get_rate(clk);
		if (rate >= 100000000)
			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
		else
			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
	} else {
		/* Initialize CORE_REFCLK1 to the same clock reference to maintain old DT compatibility */
		wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
	}

	clk = devm_clk_get(dev, "ext_ref_clk");
	if (IS_ERR(clk)) {
		dev_err(dev, "ext_ref_clk clock not found\n");
		ret = PTR_ERR(clk);
		return ret;
	}

	wiz->input_clks[WIZ_EXT_REFCLK] = clk;
	/* Initialize EXT_REFCLK1 to the same clock reference to maintain old DT compatibility */
	wiz->input_clks[WIZ_EXT_REFCLK1] = clk;

	rate = clk_get_rate(clk);
	if (rate >= 100000000)
		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
	else
		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);

	return 0;
}

static ofnode get_child_by_name(struct udevice *dev, const char *name)
{
	int l = strlen(name);
	ofnode node = dev_read_first_subnode(dev);

	while (ofnode_valid(node)) {
		const char *child_name = ofnode_get_name(node);

		if (!strncmp(child_name, name, l)) {
			if (child_name[l] == '\0' || child_name[l] == '@')
				return node;
		}
		node = dev_read_next_subnode(node);
	}
	return node;
}

static int j721e_wiz_bind_clocks(struct wiz *wiz)
{
	struct udevice *dev = wiz->dev;
	struct driver *wiz_clk_drv;
	int i, rc;

	wiz_clk_drv = lists_driver_lookup_name("wiz_clk");
	if (!wiz_clk_drv) {
		dev_err(dev, "Cannot find driver 'wiz_clk'\n");
		return -ENOENT;
	}

	for (i = 0; i < WIZ_DIV_NUM_CLOCKS_10G; i++) {
		rc = device_bind(dev, wiz_clk_drv, clk_div_sel[i].node_name,
				 &clk_div_sel[i], dev_ofnode(dev), NULL);
		if (rc) {
			dev_err(dev, "cannot bind driver for clock %s\n",
				clk_div_sel[i].node_name);
		}
	}

	for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
		rc = device_bind(dev, wiz_clk_drv, clk_mux_sel_10g[i].node_name,
				 &clk_mux_sel_10g[i], dev_ofnode(dev), NULL);
		if (rc) {
			dev_err(dev, "cannot bind driver for clock %s\n",
				clk_mux_sel_10g[i].node_name);
		}
	}

	return 0;
}

static int j721e_wiz_bind_of_clocks(struct wiz *wiz)
{
	struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
	struct udevice *dev = wiz->dev;
	enum wiz_type type = wiz->type;
	struct driver *div_clk_drv;
	struct driver *mux_clk_drv;
	ofnode node;
	int i, rc;

	if (type == AM64_WIZ_10G || type == J721E_WIZ_10G)
 		return j721e_wiz_bind_clocks(wiz);

	div_clk_drv = lists_driver_lookup_name("wiz_div_clk");
	if (!div_clk_drv) {
		dev_err(dev, "Cannot find driver 'wiz_div_clk'\n");
		return -ENOENT;
	}

	mux_clk_drv = lists_driver_lookup_name("wiz_mux_clk");
	if (!mux_clk_drv) {
		dev_err(dev, "Cannot find driver 'wiz_mux_clk'\n");
		return -ENOENT;
	}

	for (i = 0; i < wiz->clk_div_sel_num; i++) {
		node = get_child_by_name(dev, clk_div_sel[i].node_name);
		if (!ofnode_valid(node)) {
			dev_err(dev, "cannot find node for clock %s\n",
				clk_div_sel[i].node_name);
			continue;
		}
		rc = device_bind(dev, div_clk_drv, clk_div_sel[i].node_name,
				 &clk_div_sel[i], node, NULL);
		if (rc) {
			dev_err(dev, "cannot bind driver for clock %s\n",
				clk_div_sel[i].node_name);
		}
	}

	for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
		node = get_child_by_name(dev, clk_mux_sel[i].node_name);
		if (!ofnode_valid(node)) {
			dev_err(dev, "cannot find node for clock %s\n",
				clk_mux_sel[i].node_name);
			continue;
		}
		rc = device_bind(dev, mux_clk_drv, clk_mux_sel[i].node_name,
				 &clk_mux_sel[i], node, NULL);
		if (rc) {
			dev_err(dev, "cannot bind driver for clock %s\n",
				clk_mux_sel[i].node_name);
		}
	}

	return 0;
}

static int j721e_wiz_bind_reset(struct udevice *dev)
{
	int rc;
	struct driver *drv;

	drv = lists_driver_lookup_name("wiz-reset");
	if (!drv) {
		dev_err(dev, "Cannot find driver 'wiz-reset'\n");
		return -ENOENT;
	}

	rc = device_bind(dev, drv, "wiz-reset", NULL, dev_ofnode(dev), NULL);
	if (rc) {
		dev_err(dev, "cannot bind driver for wiz-reset\n");
		return rc;
	}

	return 0;
}

static int j721e_wiz_bind(struct udevice *dev)
{
	dm_scan_fdt_dev(dev);

	return 0;
}

static int wiz_get_lane_phy_types(struct udevice *dev, struct wiz *wiz)
{
	ofnode child, serdes;

	serdes = get_child_by_name(dev, "serdes");
	if (!ofnode_valid(serdes)) {
		dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
		return -EINVAL;
	}

	ofnode_for_each_subnode(child, serdes) {
		u32 reg, num_lanes = 1, phy_type = PHY_NONE;
		int ret, i;

		ret = ofnode_read_u32(child, "reg", &reg);
		if (ret) {
			dev_err(dev, "%s: Reading \"reg\" from failed: %d\n",
				__func__, ret);
			return ret;
		}
		ofnode_read_u32(child, "cdns,num-lanes", &num_lanes);
		ofnode_read_u32(child, "cdns,phy-type", &phy_type);

		dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
			reg, reg + num_lanes - 1, phy_type);

		for (i = reg; i < reg + num_lanes; i++) {
			wiz->lane_phy_type[i] = phy_type;
			wiz->master_lane_num[i] = reg;
		}
	}

	return 0;
}

static int j721e_wiz_probe(struct udevice *dev)
{
	struct wiz *wiz = dev_get_priv(dev);
	struct ofnode_phandle_args args;
	unsigned int val;
	int rc, i;
	ofnode node;
	struct regmap *regmap;
	u32 num_lanes;

	node = get_child_by_name(dev, "serdes");

	if (!ofnode_valid(node)) {
		dev_err(dev, "Failed to get SERDES child DT node\n");
		return -ENODEV;
	}

	rc = regmap_init_mem(node, &regmap);
	if (rc)  {
		dev_err(dev, "Failed to get memory resource\n");
		return rc;
	}
	rc = dev_read_u32(dev, "num-lanes", &num_lanes);
	if (rc) {
		dev_err(dev, "Failed to read num-lanes property\n");
		goto err_addr_to_resource;
	}

	if (num_lanes > WIZ_MAX_LANES) {
		dev_err(dev, "Cannot support %d lanes\n", num_lanes);
		goto err_addr_to_resource;
	}

	wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
						      GPIOD_IS_IN);
	if (IS_ERR(wiz->gpio_typec_dir)) {
		rc = PTR_ERR(wiz->gpio_typec_dir);
		dev_err(dev, "Failed to request typec-dir gpio: %d\n", rc);
		goto err_addr_to_resource;
	}

	rc = dev_read_phandle_with_args(dev, "power-domains", "#power-domain-cells", 0, 0, &args);
	if (rc) {
		dev_err(dev, "Failed to get power domain: %d\n", rc);
		goto err_addr_to_resource;
	}

	wiz->id = args.args[0];
	wiz->regmap = regmap;
	wiz->num_lanes = num_lanes;
	wiz->dev = dev;
	wiz->clk_div_sel = clk_div_sel;

	wiz->data = (struct wiz_data *)dev_get_driver_data(dev);
	wiz->type = wiz->data->type;

	wiz->clk_mux_sel = (struct wiz_clk_mux_sel *)wiz->data->clk_mux_sel;
	wiz->clk_div_sel_num = wiz->data->clk_div_sel_num;

	rc = wiz_get_lane_phy_types(dev, wiz);
	if (rc) {
		dev_err(dev, "Failed to get lane PHY types\n");
		goto err_addr_to_resource;
	}

	rc = wiz_regfield_init(wiz);
	if (rc) {
		dev_err(dev, "Failed to initialize regfields\n");
		goto err_addr_to_resource;
	}

	for (i = 0; i < wiz->num_lanes; i++) {
		regmap_field_read(wiz->p_enable[i], &val);
		if (val & (P_ENABLE | P_ENABLE_FORCE)) {
			dev_err(dev, "SERDES already configured\n");
			rc = -EBUSY;
			goto err_addr_to_resource;
		}
	}

	rc = j721e_wiz_bind_of_clocks(wiz);
	if (rc) {
		dev_err(dev, "Failed to bind clocks\n");
		goto err_addr_to_resource;
	}

	rc = j721e_wiz_bind_reset(dev);
	if (rc) {
		dev_err(dev, "Failed to bind reset\n");
		goto err_addr_to_resource;
	}

	rc = wiz_clock_init(wiz);
	if (rc) {
		dev_warn(dev, "Failed to initialize clocks\n");
		goto err_addr_to_resource;
	}

	rc = wiz_init(wiz);
	if (rc) {
		dev_err(dev, "WIZ initialization failed\n");
		goto err_addr_to_resource;
	}

	return 0;

err_addr_to_resource:
	free(regmap);

	return rc;
}

static int j721e_wiz_remove(struct udevice *dev)
{
	struct wiz *wiz = dev_get_priv(dev);

	if (wiz->regmap)
		free(wiz->regmap);

	return 0;
}

static const struct udevice_id j721e_wiz_ids[] = {
	{
		.compatible = "ti,j721e-wiz-16g", .data = (ulong)&j721e_16g_data,
	},
	{
		.compatible = "ti,j721e-wiz-10g", .data = (ulong)&j721e_10g_data,
	},
	{
		.compatible = "ti,am64-wiz-10g", .data = (ulong)&am64_10g_data,
	},
	{
		.compatible = "ti,j784s4-wiz-10g", .data = (ulong)&j784s4_wiz_10g,
	},
	{
		.compatible = "ti,j721s2-wiz-10g", .data = (ulong)&j721s2_10g_data,
	},
	{}
};

U_BOOT_DRIVER(phy_j721e_wiz) = {
	.name		= "phy-j721e-wiz",
	.id		= UCLASS_NOP,
	.of_match	= j721e_wiz_ids,
	.bind		= j721e_wiz_bind,
	.probe		= j721e_wiz_probe,
	.remove		= j721e_wiz_remove,
	.priv_auto	= sizeof(struct wiz),
	.flags		= DM_FLAG_LEAVE_PD_ON,
};

am65-cpsw-nuss.c looks the following:

// SPDX-License-Identifier: GPL-2.0+
/*
 * Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
 *
 * Copyright (C) 2019, Texas Instruments, Incorporated
 *
 */

#include <common.h>
#include <malloc.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <dma-uclass.h>
#include <dm/of_access.h>
#include <miiphy.h>
#include <net.h>
#include <phy.h>
#include <power-domain.h>
#include <regmap.h>
#include <soc.h>
#include <syscon.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/soc/ti/ti-udma.h>

#include "cpsw_mdio.h"

#define AM65_CPSW_CPSWNU_MAX_PORTS 9

#define DEFAULT_GPIO_RESET_DELAY		10

#define AM65_CPSW_SS_BASE		0x0
#define AM65_CPSW_SGMII_BASE	0x100
#define AM65_CPSW_MDIO_BASE	0xf00
#define AM65_CPSW_XGMII_BASE	0x2100
#define AM65_CPSW_CPSW_NU_BASE	0x20000
#define AM65_CPSW_CPSW_NU_ALE_BASE 0x1e000

#define AM65_CPSW_CPSW_NU_PORTS_OFFSET	0x1000
#define AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET	0x330

#define AM65_CPSW_MDIO_BUS_FREQ_DEF 1000000

#define AM65_CPSW_CTL_REG		0x4
#define AM65_CPSW_SGMII_CONTROL_REG	0x10
#define AM65_CPSW_STAT_PORT_EN_REG	0x14
#define AM65_CPSW_PTYPE_REG		0x18

#define AM65_CPSW_CTL_REG_P0_ENABLE			BIT(2)
#define AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE		BIT(13)
#define AM65_CPSW_CTL_REG_P0_RX_PAD			BIT(14)

#define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE	BIT(0)

#define AM65_CPSW_P0_FLOW_ID_REG			0x8
#define AM65_CPSW_PN_RX_MAXLEN_REG		0x24
#define AM65_CPSW_PN_REG_SA_L			0x308
#define AM65_CPSW_PN_REG_SA_H			0x30c

#define AM65_CPSW_ALE_CTL_REG			0x8
#define AM65_CPSW_ALE_CTL_REG_ENABLE		BIT(31)
#define AM65_CPSW_ALE_CTL_REG_RESET_TBL		BIT(30)
#define AM65_CPSW_ALE_CTL_REG_BYPASS		BIT(4)
#define AM65_CPSW_ALE_PN_CTL_REG(x)		(0x40 + (x) * 4)
#define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD	0x3
#define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY	BIT(11)

#define AM65_CPSW_ALE_THREADMAPDEF_REG		0x134
#define AM65_CPSW_ALE_DEFTHREAD_EN		BIT(15)

#define AM65_CPSW_MACSL_CTL_REG			0x0
#define AM65_CPSW_MACSL_CTL_REG_IFCTL_A		BIT(15)
#define AM65_CPSW_MACSL_CTL_EXT_EN		BIT(18)
#define AM65_CPSW_MACSL_CTL_REG_GIG		BIT(7)
#define AM65_CPSW_MACSL_CTL_REG_GMII_EN		BIT(5)
#define AM65_CPSW_MACSL_CTL_REG_LOOPBACK	BIT(1)
#define AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX	BIT(0)
#define AM65_CPSW_MACSL_RESET_REG		0x8
#define AM65_CPSW_MACSL_RESET_REG_RESET		BIT(0)
#define AM65_CPSW_MACSL_STATUS_REG		0x4
#define AM65_CPSW_MACSL_RESET_REG_PN_IDLE	BIT(31)
#define AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE	BIT(30)
#define AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE	BIT(29)
#define AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE	BIT(28)
#define AM65_CPSW_MACSL_RESET_REG_IDLE_MASK \
	(AM65_CPSW_MACSL_RESET_REG_PN_IDLE | \
	 AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE | \
	 AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE | \
	 AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE)

#define AM65_CPSW_CPPI_PKT_TYPE			0x7

struct am65_cpsw_port {
	fdt_addr_t	port_base;
	fdt_addr_t	sgmii_base;
	fdt_addr_t	macsl_base;
	bool		disabled;
	u32		mac_control;
};

struct am65_cpsw_common {
	struct udevice		*dev;
	fdt_addr_t		ss_base;
	fdt_addr_t		cpsw_base;
	fdt_addr_t		mdio_base;
	fdt_addr_t		ale_base;

	struct clk		fclk;
	struct power_domain	pwrdmn;

	u32			port_num;
	struct am65_cpsw_port	ports[AM65_CPSW_CPSWNU_MAX_PORTS];
	u32			qsgmii_main_ports;
	struct mii_dev		*bus;
	u32			bus_freq;
	struct gpio_desc	mdio_gpio_reset;
	u32			reset_delay_us;
	u32			reset_post_delay_us;

	struct dma		dma_tx;
	struct dma		dma_rx;
	u32			rx_next;
	u32			rx_pend;
	bool			started;
};

struct am65_cpsw_priv {
	struct udevice		*dev;
	struct am65_cpsw_common	*cpsw_common;
	u32			port_id;

	struct phy_device	*phydev;
	bool			has_phy;
	ofnode			phy_node;
	u32			phy_addr;

	bool			mdio_manual_mode;
};

#ifdef PKTSIZE_ALIGN
#define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
#else
#define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
#endif

#ifdef PKTBUFSRX
#define UDMA_RX_DESC_NUM PKTBUFSRX
#else
#define UDMA_RX_DESC_NUM 4
#endif

#define mac_hi(mac)	(((mac)[0] << 0) | ((mac)[1] << 8) |    \
			 ((mac)[2] << 16) | ((mac)[3] << 24))
#define mac_lo(mac)	(((mac)[4] << 0) | ((mac)[5] << 8))

static void am65_cpsw_set_sl_mac(struct am65_cpsw_port *slave,
				 unsigned char *addr)
{
	writel(mac_hi(addr),
	       slave->port_base + AM65_CPSW_PN_REG_SA_H);
	writel(mac_lo(addr),
	       slave->port_base + AM65_CPSW_PN_REG_SA_L);
}

int am65_cpsw_macsl_reset(struct am65_cpsw_port *slave)
{
	u32 i = 100;

	/* Set the soft reset bit */
	writel(AM65_CPSW_MACSL_RESET_REG_RESET,
	       slave->macsl_base + AM65_CPSW_MACSL_RESET_REG);

	while ((readl(slave->macsl_base + AM65_CPSW_MACSL_RESET_REG) &
		AM65_CPSW_MACSL_RESET_REG_RESET) && i--)
		cpu_relax();

	/* Timeout on the reset */
	return i;
}

static int am65_cpsw_macsl_wait_for_idle(struct am65_cpsw_port *slave)
{
	u32 i = 100;

	while ((readl(slave->macsl_base + AM65_CPSW_MACSL_STATUS_REG) &
		AM65_CPSW_MACSL_RESET_REG_IDLE_MASK) && i--)
		cpu_relax();

	return i;
}

static int am65_cpsw_update_link(struct am65_cpsw_priv *priv)
{
	struct am65_cpsw_common	*common = priv->cpsw_common;
	struct am65_cpsw_port *port = &common->ports[priv->port_id];
	struct phy_device *phy = priv->phydev;
	u32 mac_control = 0;

	if (phy->link) { /* link up */
		mac_control = /*AM65_CPSW_MACSL_CTL_REG_LOOPBACK |*/
			      AM65_CPSW_MACSL_CTL_REG_GMII_EN;
		if (phy->speed == 1000)
			mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG;
		if (phy->speed == 10 && phy_interface_is_rgmii(phy))
			/* Can be used with in band mode only */
			mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN;
		if (phy->duplex == DUPLEX_FULL)
			mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
		if (phy->speed == 100)
			mac_control |= AM65_CPSW_MACSL_CTL_REG_IFCTL_A;
	}

	if (mac_control == port->mac_control)
		goto out;

	if (mac_control) {
		printf("link up on port %d, speed %d, %s duplex\n",
		       priv->port_id, phy->speed,
		       (phy->duplex == DUPLEX_FULL) ? "full" : "half");
	} else {
		printf("link down on port %d\n", priv->port_id);
	}

	writel(mac_control, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
	port->mac_control = mac_control;

out:
	return phy->link;
}

#define AM65_GMII_SEL_PORT_OFFS(x)	(0x4 * ((x) - 1))

#define AM65_GMII_SEL_MODE_MII		0
#define AM65_GMII_SEL_MODE_RMII		1
#define AM65_GMII_SEL_MODE_RGMII	2
#define AM65_GMII_SEL_MODE_SGMII	3
#define AM65_GMII_SEL_MODE_QSGMII	4
#define AM65_GMII_SEL_MODE_QSGMII_SUB	6

#define AM65_GMII_SEL_RGMII_IDMODE	BIT(4)

static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
				 phy_interface_t phy_mode)
{
	struct udevice *dev = priv->dev;
	u32 offset, reg, phandle;
	bool rgmii_id = false;
	fdt_addr_t gmii_sel;
	u32 mode = 0;
	ofnode node;
	int ret;

	ret = ofnode_read_u32(dev_ofnode(dev), "phys", &phandle);
	if (ret)
		return ret;

	ret = ofnode_read_u32_index(dev_ofnode(dev), "phys", 1, &offset);
	if (ret)
		return ret;

	node = ofnode_get_by_phandle(phandle);
	if (!ofnode_valid(node))
		return -ENODEV;

	gmii_sel = ofnode_get_addr(node);
	if (gmii_sel == FDT_ADDR_T_NONE)
		return -ENODEV;

	gmii_sel += AM65_GMII_SEL_PORT_OFFS(offset);
	reg = readl(gmii_sel);

	dev_dbg(dev, "old gmii_sel: %08x\n", reg);

	switch (phy_mode) {
	case PHY_INTERFACE_MODE_RMII:
		mode = AM65_GMII_SEL_MODE_RMII;
		break;

	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_RXID:
		mode = AM65_GMII_SEL_MODE_RGMII;
		break;

	case PHY_INTERFACE_MODE_RGMII_ID:
	case PHY_INTERFACE_MODE_RGMII_TXID:
		mode = AM65_GMII_SEL_MODE_RGMII;
		rgmii_id = true;
		break;
		
	case PHY_INTERFACE_MODE_SGMII:
		mode = AM65_GMII_SEL_MODE_SGMII;
		break;

	default:
		dev_warn(dev,
			 "Unsupported PHY mode: %u. Defaulting to MII.\n",
			 phy_mode);
		/* fallthrough */
	case PHY_INTERFACE_MODE_MII:
		mode = AM65_GMII_SEL_MODE_MII;
		break;
	};

	if (rgmii_id)
		mode |= AM65_GMII_SEL_RGMII_IDMODE;

	reg = mode;
	dev_dbg(dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n",
		phy_mode, reg);
	writel(reg, gmii_sel);

	reg = readl(gmii_sel);
	if (reg != mode) {
		dev_err(dev,
			"gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n",
			mode, reg);
		return 0;
	}

	return 0;
}

static int am65_cpsw_start(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct am65_cpsw_priv *priv = dev_get_priv(dev);
	struct am65_cpsw_common	*common = priv->cpsw_common;
	struct am65_cpsw_port *port = &common->ports[priv->port_id];
	struct am65_cpsw_port *port0 = &common->ports[0];
	struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data;
	int ret, i;

	ret = power_domain_on(&common->pwrdmn);
	if (ret) {
		dev_err(dev, "power_domain_on() failed %d\n", ret);
		goto out;
	}

	ret = clk_enable(&common->fclk);
	if (ret) {
		dev_err(dev, "clk enabled failed %d\n", ret);
		goto err_off_pwrdm;
	}

	common->rx_next = 0;
	common->rx_pend = 0;
	ret = dma_get_by_name(common->dev, "tx0", &common->dma_tx);
	if (ret) {
		dev_err(dev, "TX dma get failed %d\n", ret);
		goto err_off_clk;
	}
	ret = dma_get_by_name(common->dev, "rx", &common->dma_rx);
	if (ret) {
		dev_err(dev, "RX dma get failed %d\n", ret);
		goto err_free_tx;
	}

	for (i = 0; i < UDMA_RX_DESC_NUM; i++) {
		ret = dma_prepare_rcv_buf(&common->dma_rx,
					  net_rx_packets[i],
					  UDMA_RX_BUF_SIZE);
		if (ret) {
			dev_err(dev, "RX dma add buf failed %d\n", ret);
			goto err_free_tx;
		}
	}

	ret = dma_enable(&common->dma_tx);
	if (ret) {
		dev_err(dev, "TX dma_enable failed %d\n", ret);
		goto err_free_rx;
	}
	ret = dma_enable(&common->dma_rx);
	if (ret) {
		dev_err(dev, "RX dma_enable failed %d\n", ret);
		goto err_dis_tx;
	}

	/* Control register */
	writel(AM65_CPSW_CTL_REG_P0_ENABLE |
	       AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE |
	       AM65_CPSW_CTL_REG_P0_RX_PAD,
	       common->cpsw_base + AM65_CPSW_CTL_REG);

	/* disable priority elevation */
	writel(0, common->cpsw_base + AM65_CPSW_PTYPE_REG);

	/* enable statistics */
	writel(BIT(0) | BIT(priv->port_id),
	       common->cpsw_base + AM65_CPSW_STAT_PORT_EN_REG);

	/* Port 0  length register */
	writel(PKTSIZE_ALIGN, port0->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);

	/* set base flow_id */
	dma_get_cfg(&common->dma_rx, 0, (void **)&dma_rx_cfg_data);
	writel(dma_rx_cfg_data->flow_id_base,
	       port0->port_base + AM65_CPSW_P0_FLOW_ID_REG);
	dev_info(dev, "K3 CPSW: rflow_id_base: %u\n",
		 dma_rx_cfg_data->flow_id_base);
		 
	if (pdata->phy_interface == PHY_INTERFACE_MODE_SGMII ||
	    pdata->phy_interface == PHY_INTERFACE_MODE_QSGMII)
		writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,
		       port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);

	/* Reset and enable the ALE */
	writel(AM65_CPSW_ALE_CTL_REG_ENABLE | AM65_CPSW_ALE_CTL_REG_RESET_TBL |
	       AM65_CPSW_ALE_CTL_REG_BYPASS,
	       common->ale_base + AM65_CPSW_ALE_CTL_REG);

	/* port 0 put into forward mode */
	writel(AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
	       common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));

	writel(AM65_CPSW_ALE_DEFTHREAD_EN,
	       common->ale_base + AM65_CPSW_ALE_THREADMAPDEF_REG);

	/* PORT x configuration */

	/* Port x Max length register */
	writel(PKTSIZE_ALIGN, port->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);

	/* Port x set mac */
	am65_cpsw_set_sl_mac(port, pdata->enetaddr);

	/* Port x ALE: mac_only, Forwarding */
	writel(AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY |
	       AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
	       common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));

	port->mac_control = 0;
	if (!am65_cpsw_macsl_reset(port)) {
		dev_err(dev, "mac_sl reset failed\n");
		ret = -EFAULT;
		goto err_dis_rx;
	}

	ret = phy_startup(priv->phydev);
	if (ret) {
		dev_err(dev, "phy_startup failed\n");
		goto err_dis_rx;
	}

	ret = am65_cpsw_update_link(priv);
	if (!ret) {
		ret = -ENODEV;
		goto err_phy_shutdown;
	}

	common->started = true;

	return 0;

err_phy_shutdown:
	phy_shutdown(priv->phydev);
err_dis_rx:
	/* disable ports */
	writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
	writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
	if (!am65_cpsw_macsl_wait_for_idle(port))
		dev_err(dev, "mac_sl idle timeout\n");
	writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
	writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
	writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);

	dma_disable(&common->dma_rx);
err_dis_tx:
	dma_disable(&common->dma_tx);
err_free_rx:
	dma_free(&common->dma_rx);
err_free_tx:
	dma_free(&common->dma_tx);
err_off_clk:
	clk_disable(&common->fclk);
err_off_pwrdm:
	power_domain_off(&common->pwrdmn);
out:
	dev_err(dev, "%s end error\n", __func__);

	return ret;
}

static int am65_cpsw_send(struct udevice *dev, void *packet, int length)
{
	struct am65_cpsw_priv *priv = dev_get_priv(dev);
	struct am65_cpsw_common	*common = priv->cpsw_common;
	struct ti_udma_drv_packet_data packet_data;
	int ret;

	packet_data.pkt_type = AM65_CPSW_CPPI_PKT_TYPE;
	packet_data.dest_tag = priv->port_id;
	ret = dma_send(&common->dma_tx, packet, length, &packet_data);
	if (ret) {
		dev_err(dev, "TX dma_send failed %d\n", ret);
		return ret;
	}

	return 0;
}

static int am65_cpsw_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct am65_cpsw_priv *priv = dev_get_priv(dev);
	struct am65_cpsw_common	*common = priv->cpsw_common;

	/* try to receive a new packet */
	return dma_receive(&common->dma_rx, (void **)packetp, NULL);
}

static int am65_cpsw_free_pkt(struct udevice *dev, uchar *packet, int length)
{
	struct am65_cpsw_priv *priv = dev_get_priv(dev);
	struct am65_cpsw_common	*common = priv->cpsw_common;
	int ret;

	if (length > 0) {
		u32 pkt = common->rx_next % UDMA_RX_DESC_NUM;

		ret = dma_prepare_rcv_buf(&common->dma_rx,
					  net_rx_packets[pkt],
					  UDMA_RX_BUF_SIZE);
		if (ret)
			dev_err(dev, "RX dma free_pkt failed %d\n", ret);
		common->rx_next++;
	}

	return 0;
}

static void am65_cpsw_stop(struct udevice *dev)
{
	struct am65_cpsw_priv *priv = dev_get_priv(dev);
	struct am65_cpsw_common *common = priv->cpsw_common;
	struct am65_cpsw_port *port = &common->ports[priv->port_id];

	if (!common->started)
		return;

	phy_shutdown(priv->phydev);

	writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
	writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
	if (!am65_cpsw_macsl_wait_for_idle(port))
		dev_err(dev, "mac_sl idle timeout\n");
	writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
	writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
	writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);

	dma_disable(&common->dma_tx);
	dma_free(&common->dma_tx);

	dma_disable(&common->dma_rx);
	dma_free(&common->dma_rx);

	common->started = false;
}

static int am65_cpsw_am654_get_efuse_macid(struct udevice *dev,
					   int slave, u8 *mac_addr)
{
	u32 mac_lo, mac_hi, offset;
	struct regmap *syscon;
	int ret;

	syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-efuse");
	if (IS_ERR(syscon)) {
		if (PTR_ERR(syscon) == -ENODEV)
			return 0;
		return PTR_ERR(syscon);
	}

	ret = dev_read_u32_index(dev, "ti,syscon-efuse", 1, &offset);
	if (ret)
		return ret;

	regmap_read(syscon, offset, &mac_lo);
	regmap_read(syscon, offset + 4, &mac_hi);

	mac_addr[0] = (mac_hi >> 8) & 0xff;
	mac_addr[1] = mac_hi & 0xff;
	mac_addr[2] = (mac_lo >> 24) & 0xff;
	mac_addr[3] = (mac_lo >> 16) & 0xff;
	mac_addr[4] = (mac_lo >> 8) & 0xff;
	mac_addr[5] = mac_lo & 0xff;

	return 0;
}

static int am65_cpsw_read_rom_hwaddr(struct udevice *dev)
{
	struct am65_cpsw_priv *priv = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);

	am65_cpsw_am654_get_efuse_macid(dev,
					priv->port_id,
					pdata->enetaddr);

	return 0;
}

static const struct eth_ops am65_cpsw_ops = {
	.start		= am65_cpsw_start,
	.send		= am65_cpsw_send,
	.recv		= am65_cpsw_recv,
	.free_pkt	= am65_cpsw_free_pkt,
	.stop		= am65_cpsw_stop,
	.read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
};

static const struct soc_attr k3_mdio_soc_data[] = {
	{ .family = "AM62X", .revision = "SR1.0" },
	{ .family = "AM64X", .revision = "SR1.0" },
	{ .family = "AM64X", .revision = "SR2.0" },
	{ .family = "AM65X", .revision = "SR1.0" },
	{ .family = "AM65X", .revision = "SR2.0" },
	{ .family = "J7200", .revision = "SR1.0" },
	{ .family = "J7200", .revision = "SR2.0" },
	{ .family = "J721E", .revision = "SR1.0" },
	{ .family = "J721E", .revision = "SR1.1" },
	{ .family = "J721S2", .revision = "SR1.0" },
	{ /* sentinel */ },
};

static ofnode am65_cpsw_find_mdio(ofnode parent)
{
	ofnode node;

	ofnode_for_each_subnode(node, parent)
		if (ofnode_device_is_compatible(node, "ti,cpsw-mdio"))
			return node;

	return ofnode_null();
}

static int am65_cpsw_mdio_setup(struct udevice *dev)
{
	struct am65_cpsw_priv *priv = dev_get_priv(dev);
	struct am65_cpsw_common	*cpsw_common = priv->cpsw_common;
	struct udevice *mdio_dev;
	ofnode mdio;
	int ret;

	mdio = am65_cpsw_find_mdio(dev_ofnode(cpsw_common->dev));
	if (!ofnode_valid(mdio))
		return 0;

	/*
	 * The MDIO controller is represented in the DT binding by a
	 * subnode of the MAC controller.
	 *
	 * We don't have a DM driver for the MDIO device yet, and thus any
	 * pinctrl setting on its node will be ignored.
	 *
	 * However, we do need to make sure the pins states tied to the
	 * MDIO node are configured properly. Fortunately, the core DM
	 * does that for use when we get a device, so we can work around
	 * that whole issue by just requesting a dummy MDIO driver to
	 * probe, and our pins will get muxed.
	 */
	ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdio_dev);
	if (ret)
		return ret;

	return 0;
}

static int am65_cpsw_mdio_init(struct udevice *dev)
{
	struct am65_cpsw_priv *priv = dev_get_priv(dev);
	struct am65_cpsw_common	*cpsw_common = priv->cpsw_common;
	int ret;

	if (!priv->has_phy || cpsw_common->bus)
		return 0;
		
	if (dm_gpio_is_valid(&cpsw_common->mdio_gpio_reset)) {
		dm_gpio_set_value(&cpsw_common->mdio_gpio_reset, 1);
		udelay(cpsw_common->reset_delay_us);
		dm_gpio_set_value(&cpsw_common->mdio_gpio_reset, 0);
		if (cpsw_common->reset_post_delay_us > 0)
			udelay(cpsw_common->reset_post_delay_us);
	}

	ret = am65_cpsw_mdio_setup(dev);
	if (ret)
		return ret;

	cpsw_common->bus = cpsw_mdio_init(dev->name,
					  cpsw_common->mdio_base,
					  cpsw_common->bus_freq,
					  clk_get_rate(&cpsw_common->fclk),
					  priv->mdio_manual_mode);
	if (!cpsw_common->bus)
		return -EFAULT;

	return 0;
}

static int am65_cpsw_phy_init(struct udevice *dev)
{
	struct am65_cpsw_priv *priv = dev_get_priv(dev);
	struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct phy_device *phydev;
	u32 supported = PHY_GBIT_FEATURES;
	int ret;

	phydev = phy_connect(cpsw_common->bus,
			     priv->phy_addr,
			     priv->dev,
			     pdata->phy_interface);

	if (!phydev) {
		dev_err(dev, "phy_connect() failed\n");
		return -ENODEV;
	}

	phydev->supported &= supported;
	if (pdata->max_speed) {
		ret = phy_set_supported(phydev, pdata->max_speed);
		if (ret)
			return ret;
	}
	phydev->advertising = phydev->supported;

	if (ofnode_valid(priv->phy_node))
		phydev->node = priv->phy_node;

	priv->phydev = phydev;
	ret = phy_config(phydev);
	if (ret < 0)
		pr_err("phy_config() failed: %d", ret);

	return ret;
}

static int am65_cpsw_ofdata_parse_phy(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct am65_cpsw_priv *priv = dev_get_priv(dev);
	struct ofnode_phandle_args out_args;
	int ret = 0;

	dev_read_u32(dev, "reg", &priv->port_id);

	pdata->phy_interface = dev_read_phy_mode(dev);
	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
		dev_err(dev, "Invalid PHY mode, port %u\n", priv->port_id);
		return -EINVAL;
	}

	dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed);
	if (pdata->max_speed)
		dev_err(dev, "Port %u speed froced to %uMbit\n",
			priv->port_id, pdata->max_speed);

	priv->has_phy  = true;
	ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
					     NULL, 0, 0, &out_args);
	if (ret) {
		dev_err(dev, "can't parse phy-handle port %u (%d)\n",
			priv->port_id, ret);
		priv->has_phy  = false;
		ret = 0;
	}

	priv->phy_node = out_args.node;
	if (priv->has_phy) {
		ret = ofnode_read_u32(priv->phy_node, "reg", &priv->phy_addr);
		if (ret) {
			dev_err(dev, "failed to get phy_addr port %u (%d)\n",
				priv->port_id, ret);
			goto out;
		}
	}

out:
	return ret;
}

static int am65_cpsw_port_probe(struct udevice *dev)
{
	struct am65_cpsw_priv *priv = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct am65_cpsw_common *cpsw_common;
	char portname[15];
	int ret;

	priv->dev = dev;

	cpsw_common = dev_get_priv(dev->parent);
	priv->cpsw_common = cpsw_common;

	sprintf(portname, "%s%s", dev->parent->name, dev->name);
	device_set_name(dev, portname);

	priv->mdio_manual_mode = false;
	if (soc_device_match(k3_mdio_soc_data))
		priv->mdio_manual_mode = true;

	ret = am65_cpsw_ofdata_parse_phy(dev);
	if (ret)
		goto out;

	ret = am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface);
	if (ret)
		goto out;

	ret = am65_cpsw_mdio_init(dev);
	if (ret)
		goto out;

	ret = am65_cpsw_phy_init(dev);
	if (ret)
		goto out;
out:
	return ret;
}

static int am65_cpsw_probe_nuss(struct udevice *dev)
{
	struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
	ofnode ports_np, node, mdio_np;
	int ret, i;
	struct udevice *port_dev;

	cpsw_common->dev = dev;
	cpsw_common->ss_base = dev_read_addr(dev);
	if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
		return -EINVAL;

	ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
	if (ret) {
		dev_err(dev, "failed to get pwrdmn: %d\n", ret);
		return ret;
	}

	ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
	if (ret) {
		power_domain_free(&cpsw_common->pwrdmn);
		dev_err(dev, "failed to get clock %d\n", ret);
		return ret;
	}

	cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
	cpsw_common->ale_base = cpsw_common->cpsw_base +
				AM65_CPSW_CPSW_NU_ALE_BASE;
	cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE;
	
	/* get bus level PHY reset GPIO details */
	mdio_np = dev_read_subnode(dev, "mdio");
	if (!ofnode_valid(mdio_np)) {
		ret = -ENOENT;
		goto out;
	}

	cpsw_common->reset_delay_us = ofnode_read_u32_default(mdio_np,
						"reset-delay-us",
						DEFAULT_GPIO_RESET_DELAY);
	cpsw_common->reset_post_delay_us = ofnode_read_u32_default(mdio_np,
						"reset-post-delay-us", 0);
	ret = gpio_request_by_name_nodev(mdio_np, "reset-gpios", 0,
					 &cpsw_common->mdio_gpio_reset,
					 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);

	ports_np = dev_read_subnode(dev, "ethernet-ports");
	if (!ofnode_valid(ports_np)) {
		ret = -ENOENT;
		goto out;
	}

	ofnode_for_each_subnode(node, ports_np) {
		const char *node_name;
		u32 port_id;
		bool disabled;

		node_name = ofnode_get_name(node);

		disabled = !ofnode_is_enabled(node);

		ret = ofnode_read_u32(node, "reg", &port_id);
		if (ret) {
			dev_err(dev, "%s: failed to get port_id (%d)\n",
				node_name, ret);
			goto out;
		}

		if (port_id >= AM65_CPSW_CPSWNU_MAX_PORTS) {
			dev_err(dev, "%s: invalid port_id (%d)\n",
				node_name, port_id);
			ret = -EINVAL;
			goto out;
		}
		cpsw_common->port_num++;

		if (!port_id)
			continue;

		cpsw_common->ports[port_id].disabled = disabled;
		if (disabled)
			continue;

		ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev);
		if (ret)
			dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(node));
	}

	for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
		struct am65_cpsw_port *port = &cpsw_common->ports[i];

		port->sgmii_base = cpsw_common->ss_base +
					(AM65_CPSW_SGMII_BASE * i);
		port->port_base = cpsw_common->cpsw_base +
				  AM65_CPSW_CPSW_NU_PORTS_OFFSET +
				  (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
		port->macsl_base = port->port_base +
				   AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
	}

	cpsw_common->bus_freq =
			dev_read_u32_default(dev, "bus_freq",
					     AM65_CPSW_MDIO_BUS_FREQ_DEF);

	dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u mdio_freq:%u\n",
		 readl(cpsw_common->ss_base),
		 readl(cpsw_common->cpsw_base),
		 readl(cpsw_common->ale_base),
		 cpsw_common->port_num,
		 cpsw_common->bus_freq);

out:
	clk_free(&cpsw_common->fclk);
	power_domain_free(&cpsw_common->pwrdmn);
	return ret;
}

static const struct udevice_id am65_cpsw_nuss_ids[] = {
	{ .compatible = "ti,am654-cpsw-nuss" },
	{ .compatible = "ti,j721e-cpsw-nuss" },
	{ .compatible = "ti,am642-cpsw-nuss" },
	{ }
};

U_BOOT_DRIVER(am65_cpsw_nuss) = {
	.name	= "am65_cpsw_nuss",
	.id	= UCLASS_MISC,
	.of_match = am65_cpsw_nuss_ids,
	.probe	= am65_cpsw_probe_nuss,
	.priv_auto = sizeof(struct am65_cpsw_common),
};

U_BOOT_DRIVER(am65_cpsw_nuss_port) = {
	.name	= "am65_cpsw_nuss_port",
	.id	= UCLASS_ETH,
	.probe	= am65_cpsw_port_probe,
	.ops	= &am65_cpsw_ops,
	.priv_auto	= sizeof(struct am65_cpsw_priv),
	.plat_auto	= sizeof(struct eth_pdata),
	.flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE,
};

static const struct udevice_id am65_cpsw_mdio_ids[] = {
	{ .compatible = "ti,cpsw-mdio" },
	{ }
};

U_BOOT_DRIVER(am65_cpsw_mdio) = {
	.name		= "am65_cpsw_mdio",
	.id		= UCLASS_MDIO,
	.of_match	= am65_cpsw_mdio_ids,
};

And another additional information, since the issue seems to be related to clocking: We are using 25 MHz external oscillator (instead of 19.2 MHz) as main clock source for TDA4.

Hi Felix,

And have you made appropriate changes for the same in the dm firmware?

Are you able to boot to the kernel. We can check the clock values using k3conf utility from there.

Regards,
Tanmay

Hi Tanmay,

is dm firmware = MCU1_0 firmware? And which appropriate changes are you referring to?

I am able to boot to kernel. I deactivated all Ethernet/SERDES4 related device tree nodes. This is the output of k3conf for SERDES4:

root@e3g-e3mn:~# k3conf dump clock 297
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.2--v09.01.02 (Kool Koala))') |
|------------------------------------------------------------------------------|

|----------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                            | Status          | Clock Frequency |
|----------------------------------------------------------------------------------------------------------------------------------|
|   297     |     0    | DEV_SERDES_10G0_IP1_LN3_TXCLK                                         | CLK_STATE_READY | 0               |
|   297     |     1    | DEV_SERDES_10G0_CLK                                                   | CLK_STATE_READY | 125000000       |
|   297     |     2    | DEV_SERDES_10G0_IP3_LN2_TXCLK                                         | CLK_STATE_READY | 0               |
|   297     |     3    | DEV_SERDES_10G0_IP1_LN2_TXCLK                                         | CLK_STATE_READY | 0               |
|   297     |     4    | DEV_SERDES_10G0_IP1_LN0_TXCLK                                         | CLK_STATE_READY | 0               |
|   297     |     5    | DEV_SERDES_10G0_IP3_LN1_TXCLK                                         | CLK_STATE_READY | 0               |
|   297     |     6    | DEV_SERDES_10G0_IP3_LN3_TXCLK                                         | CLK_STATE_READY | 0               |
|   297     |     7    | DEV_SERDES_10G0_IP3_LN0_TXCLK                                         | CLK_STATE_READY | 0               |
|   297     |     8    | DEV_SERDES_10G0_IP1_LN1_TXCLK                                         | CLK_STATE_READY | 0               |
|   297     |     9    | DEV_SERDES_10G0_CORE_REF_CLK                                          | CLK_STATE_READY | 100000000       |
|   297     |    10    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 25000000        |
|   297     |    11    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
|   297     |    12    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153       |
|   297     |    13    | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
|   297     |    14    | DEV_SERDES_10G0_IP1_LN1_REFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    15    | DEV_SERDES_10G0_IP1_LN2_RXCLK                                         | CLK_STATE_READY | 0               |
|   297     |    16    | DEV_SERDES_10G0_IP3_LN1_TXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    17    | DEV_SERDES_10G0_IP1_LN0_RXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    18    | DEV_SERDES_10G0_IP1_LN3_RXCLK                                         | CLK_STATE_READY | 0               |
|   297     |    19    | DEV_SERDES_10G0_IP3_LN3_RXCLK                                         | CLK_STATE_READY | 0               |
|   297     |    20    | DEV_SERDES_10G0_IP3_LN1_TXMCLK                                        | CLK_STATE_READY | 0               |
|   297     |    21    | DEV_SERDES_10G0_IP3_LN3_RXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    22    | DEV_SERDES_10G0_IP3_LN3_REFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    23    | DEV_SERDES_10G0_IP3_LN2_RXCLK                                         | CLK_STATE_READY | 0               |
|   297     |    24    | DEV_SERDES_10G0_IP1_LN0_TXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    25    | DEV_SERDES_10G0_IP3_LN3_TXMCLK                                        | CLK_STATE_READY | 0               |
|   297     |    26    | DEV_SERDES_10G0_IP3_LN1_RXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    27    | DEV_SERDES_10G0_IP3_LN0_RXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    28    | DEV_SERDES_10G0_IP1_LN1_TXMCLK                                        | CLK_STATE_READY | 0               |
|   297     |    29    | DEV_SERDES_10G0_IP1_LN1_RXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    30    | DEV_SERDES_10G0_IP3_LN3_TXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    31    | DEV_SERDES_10G0_IP1_LN3_TXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    32    | DEV_SERDES_10G0_IP1_LN3_TXMCLK                                        | CLK_STATE_READY | 0               |
|   297     |    33    | DEV_SERDES_10G0_IP3_LN1_REFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    34    | DEV_SERDES_10G0_IP3_LN0_REFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    35    | DEV_SERDES_10G0_IP1_LN3_REFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    36    | DEV_SERDES_10G0_IP3_LN0_RXCLK                                         | CLK_STATE_READY | 0               |
|   297     |    37    | DEV_SERDES_10G0_IP3_LN2_REFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    38    | DEV_SERDES_10G0_IP1_LN0_RXCLK                                         | CLK_STATE_READY | 0               |
|   297     |    39    | DEV_SERDES_10G0_IP1_LN0_REFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    40    | DEV_SERDES_10G0_IP1_LN2_RXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    41    | DEV_SERDES_10G0_IP1_LN1_TXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    42    | DEV_SERDES_10G0_IP3_LN0_TXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    43    | DEV_SERDES_10G0_REF_OUT_CLK                                           | CLK_STATE_READY | 0               |
|   297     |    44    | DEV_SERDES_10G0_IP3_LN1_RXCLK                                         | CLK_STATE_READY | 0               |
|   297     |    45    | DEV_SERDES_10G0_IP1_LN2_TXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    46    | DEV_SERDES_10G0_IP1_LN0_TXMCLK                                        | CLK_STATE_READY | 0               |
|   297     |    47    | DEV_SERDES_10G0_IP3_LN2_RXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    48    | DEV_SERDES_10G0_IP1_LN2_TXMCLK                                        | CLK_STATE_READY | 0               |
|   297     |    49    | DEV_SERDES_10G0_IP3_LN2_TXMCLK                                        | CLK_STATE_READY | 0               |
|   297     |    50    | DEV_SERDES_10G0_IP1_LN2_REFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    51    | DEV_SERDES_10G0_IP3_LN2_TXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    52    | DEV_SERDES_10G0_IP3_LN0_TXMCLK                                        | CLK_STATE_READY | 0               |
|   297     |    53    | DEV_SERDES_10G0_IP1_LN3_RXFCLK                                        | CLK_STATE_READY | 0               |
|   297     |    54    | DEV_SERDES_10G0_IP1_LN1_RXCLK                                         | CLK_STATE_READY | 0               |
|----------------------------------------------------------------------------------------------------------------------------------|

Best regards,

Felix

Hi TI, 

I just want to kindly remind of this issue.

Best regards,

Felix

PS: I was able to get Ethernet connection working on Linux. So there is no hardware issue. The remaining issue in U-Boot is I think mainly related with faulty configuration of SERDES4 instance. Do you have a working example based on PSDK Linux v09.01 with SERDES4 activated for U-Boot?

Hi TI, 

I just want to again kindly remind of this issue.

Best regards,

Felix

Following, I am also looking to get SGMII interface working in U-Boot

Hi Tanmay, 

any feedback on this issue is appreciated.

Best regards,

Felix

Just trying to avoid that this issue gets closed...

Checkout this thread. They have patches for some of the drivers and device trees, and I was able to get SGMII configured correctly for U-boot

e2e.ti.com/.../dra829v-enable-cpsw0-main-domain-ethernet-switch-in-u-boot