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AM62A7: How does AM62A7 avoid the collision problem of A53 and R5F accessing external nand flash at the same time

w j
Intellectual 275 points
Part Number: AM62A7


Hi all，

Does the AM62A7 support the hardware lock function to resolve the conflict between the A53 and R5F(MCU or DM) cores accessing external nand flash at the same time?

If hardware locks are supported, can you provide reference examples and documentation?

Thanks.

  • 0
    TI__Mastermind 48446 points

    Hello ,

    May I know why you want to use the same periperhal on A53 and R5F cores?

    Typically, when you want to use any peripheral, then decide where you want to use either A53 or R5F and mixing usage will create issues.

    We don't recommend to use the same peripheral on different cores.

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    Intellectual 275 points

    Hi，

    A53 cores need to store log files in external flash when running linux, and R5F cores need to store diagnostic information in external flash when deploying Autosar, so that A53 and R5F cores operate OSPI to access external flash at the same time

  • +1 in reply to w j
    TI__Mastermind 48446 points

    Hello, 

    For the above use case, we can't go with PC + Ospi. 

    So, when the A53 core runs, log information will be stored in the buffer and transferred this data to R5F through IPC. 

    Now R5f will write this data and diagnostic information on an external flash.

    Regards, 

    S. Anil. 

  • 0 in reply to Swargam Anil
    Intellectual 275 points

    Hi，

    Is it possible to use hardware Spinlock? Will it be a problem for R5F to operate nand flash after the A53 core has finished operating nand flash?

  • +1 in reply to w j
    TI__Mastermind 48446 points

    Hello ,

    Yes, you can use the hardware spinlock .But, when you use the same peripherals on both cores make sure that once operation is completed on any core then de initialize the Peripheral and try to do initialization in the other core this step you have to do else you will get some issues in while accessing the two peripherals in two core since resources allocation will be done properly on both cores.

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    TI__Mastermind 48446 points

    Hello,

    On AM62A there is no example on SPINLOCK, but this example is available on AM64X.

    Mostly both IPs are, same in the AM64x and AM62A.

    https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/09_01_00_41/exports/docs/api_guide_am64x/DRIVERS_SPINLOCK_PAGE.html

    Regards,

    S.Anil.

  • 0 in reply to Swargam Anil
    Intellectual 275 points

    Hi，

    Thank you very much.

    I have a few other questions here:

    1. Can SPINLOCK be used on R5F(DM or MCU) core? I can't find file spinlck.h in MCU+ SDK

    2. Does MCU R5F core support read and write nand flash? I can't find the relevant configuration modules (UDMA, OSPI, FLASH) in example.syscfg of MCU R5F core example project. How do I add these modules?

    3. Do you have sample code for PMIC chip TPS65931211RWERQ1? Is the official recommendation A53 nuclear control or R5F nuclear control?

  • +1 in reply to w j
    TI__Guru** 103090 points

    Hello w j,

    To clarify a bit more about what Anil is saying for different software instances accessing the same peripheral: our software does NOT support sharing peripherals or peripheral interfaces between multiple operating systems - DDR is the only exception I am aware of, because the circuitry of the DDR interface is specifically designed to allow multiple software instances to interact with it at the same time.

    1) There are a couple different options if you want to store data from multiple software instances on the same external memory: one option is to use inter-processor communication (IPC) to send data from one core to the core that owns the external memory, and then the core that owns the memory can do reads and writes.

    2) Technically, you could also have a core give up ownership of the peripheral during runtime by de-initializing the driver, and then have the other core initialize the peripheral so the second core can access the peripheral directly.

    3) You could look at other options, like using two different external memories, one for each OS, or using internal memory.

    TI has not tested 2), and we cannot support 2). Also, please note that spinlock is NOT supported for AM62Ax MCU+ cores as per the latest (SDK 9.1) software build sheet: https://software-dl.ti.com/mcu-plus-sdk/esd/AM62AX/09_01_00_39/exports/docs/build_sheet/am62a-sw-buildsheet.html

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Intellectual 275 points

    Hi,

    As you said using internal memory, is it rom or ram? Can you tell me its address? I'll check the technical manual. We need rom to store data

  • +1 in reply to w j
    TI__Guru** 103090 points

    Hello w j,

    Internal memory means on-chip SRAM (OCSRAM, or OCM in some places in the TRM - there is SRAM in the main domain and the wakeup domain), or the local TCM memory of the R5F subsystems. Since it is RAM, it does NOT preserve the data between power cycles.

    Regards,

    Nick