AM625: TRNG 64bits generation

Hello Koichiro Tashiro

Thank you for the query.

Is the customer board similar to the SK.

Help us understand how they are testing to compare.

Regards,

Sreenivasa

Hi Sreenivasa,

Kallikuppa Sreenivasa said:

Is the customer board similar to the SK.

The custom board is a different from SK board.

Kallikuppa Sreenivasa said:

Help us understand how they are testing to compare.

They simply checked internal timer values before and after TRNG generation and calculate the period.

Thanks and regards,
Koichiro Tashiro

Hello Koichiro Tashiro

Thank you.

Let me assign to the software expert.

Regards,

Sreenivasa

Hi Sreenivasa,

Any updates for this item?

Thanks and regards,
Koichiro Tashiro

Hello Koichiro Tashiro

Thank you.

I have assigned to the software expert. Let me reach out to the expert internally.

Regards,

Sreenivasa

Hello Koichiro,

Could you please confirm which core the customer is testing the TRNG generation time, Linux on A53 or through HSM M4 core?

The Linux SDK documentation has the below note:

This is due to the dependency on the oscillator and the performance might be different even boot to boot. But it might not be responsible for the 4 orders of magnitude difference seen here.

Has the customer tested the performance over multiple boot cycles, and multiple times in the same cycle? Please share the method of testing.

Regards,
Krithika

Hi Krithika,

The customer found configuration difference in TRNG_CONFIG register, SAMPLE_CYCLES bit field.
On SK-AM62 board, SAMPLE_CYCLES is 0x0.
On the custom board, SAMPLE_CYCLES is 0x5. If the value is changed to 0x0, TRNG generation time is the same as SK-AM62.

Questions:
Q1) What is "SAMPLE_CYCLES"? Is this reasonable these values(0x0 or 0x5) results in the 4 orders of generation time difference?

Q2) The customer uses below u-boot images.
SK-AM62: tiboot3-am62x-gp-evm.bin => TRNG is disabled as default.
Custom board : tiboot3-am62x-hs-fs-evm.bin => TRNG is enabled as default.
Is this expected?

Thanks and regards,
Koichiro Tashiro

Hello Koichiro,

Please find more details on TRNG in K3 Crypto TRM : software-dl.ti.com/.../SPRUIL3B.pdf

"Table 5-199. TRNG_CONFIG Register Field Descriptions" explains "SAMPLE_CYCLES" bit field.

Also, "2.10.4 TRNG Clock Configuration for First Random Value Generation"

Regards,
Krithika

Hi Krithika,

Thanks for the information. I will check TRM description.

Thanks and regards,
Koichiro Tashiro

Hi Krithika,

I checked TRM and understood SAMPLE_CYCLES impacts to the time for a single output generation.
0x0 and 0x5 difference results in ~13107 times difference.
But it is not clear how to determine SAMPLE_CYCLES value for each application.
Table 5-199 says below, what does it exactly mean?


Thanks and regards,
Koichiro Tashiro

Hi Krithika,

Could you reply to this item?

Thanks and regards,
Koichiro Tashiro

Any reply to this item?
The customer is still waiting for your answer.

Hello Koichiro,

The below is an excerpt from the TRNG IP Integration Manual:

The sample_div and sample_cycles fields in the TRNG_CONFIG register control the way data is sampled from the FROs (free-running oscilaltors). 
Typically these should be set to the normal operational settings (0), but setting the sample_cycles field to 1 basically allows for 
direct observation of the sampled FRO outputs without any oversampling

Regards,
Krithika

Hi Krithika,

I understood the value should be zero for normal operation, but is it still not clear when the value should be changed and how.

And below comment does not make sense to me.
"setting the sample_cycles field to 1 basically allows for direct observation of the sampled FRO outputs without any oversampling"

Thanks and regards,
Koichiro Tashiro