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AM62A3: Dynamic ODT for LPDDR4x

jun li
Prodigy 90 points
Part Number: AM62A3

I have the following questions about the dynamic ODT

1) is dynamic ODT enabled by default

2) what's the range of of the resistance values the Dynamic ODT might operate within ODT

3) Is there ODT mismatch requirement for the data bits within one byte
4) will calibration help to determine the optimal ODT resistance
Thanks
Jun
  • 0
    TI__Guru* 85820 points

    Hi Jun, 

    i don't think i know what you mean by dynamic ODT with respect to LPDDR4.  I'm only aware of dynamic ODT in DDR4.    Is there a section of the JEDEC spec you can refer to?  Are you asking about ODT in the memory, the controller, or both?  

    The ODT values for both processor and memory can be set using the DDR register configuration tool.  The values follow what is spec'ed in the JEDEC spec.  IO calibration is automatically enabled on the processor side, and can be enabled on the memory side.   This calibration adjusts the output driver impedance of the IOs and can be enabled periodically to perform the calibration dynamically.

    Regards,

    James