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Problem with pulse mode output with internals timers

Hi,

I'm using timer 2 output (TM64P2_OUT12) to trigger data conversion (external ADC). When i set timer 2 output in clock mode (TCR[CP12]=1), the output signal is ok, but when i set pulse mode (prefered for us), the output is not ok : stay always high. (i try 64 bits mode, 32 bits chained mode : no changes)

Our settings for 32 bits chained mode (150MHz internal clock source) :

PRD12=124, PRD34=5, TCR=0xB0 (timer enable continuously, pulse mode, TSTAT12 stay active for 4 timer clock), TGCR=0x1F (32 bits chained mode, TIM12&TIM34 active)

What's wrong ?

Is it possible to find an example to set timer output in pulse mode ?

Thanks

  • Ludovic,

    Some debugin suggestions are:

    -Have you tried on a different mode, the un-chained for the '12' Timer and see if it works.

    -the PWID12 TSTAT12 has to be set to 4 timer clock since that is a requirement for pulse mode, so ensure that the register is properly getting this setting correct.

    -try reducing the PRDs to something larger or smaller

    -try setting the INVOUTP12 signal to invert it and see if shows up

     

    regards,

    miguel

     

  • Hi,

    I set timer 2 in 32 unchained mode, when i set CP12=1 (clock mode), the output is ok (period=5µs and duty cycle=50% = what expected), but with CP12=0 : not possible to have any clock pulses on output.

    I tried PWID12 from 0 to 4 : no changes

    I tried INVOUTP12 : it inverts the output but no pulses (i try many time scale from 1ns/div to 10µs/div on our logical analyser but no pules :-( )

    Increasing PRD or decreasing : ok with clock mode, but no pulses in pulse mode

    What about undocumented registers located à offset 0x2c (equal to 0x290 after reset),  and 0x30 : maybe any problem whith these registers ?

    I am wondering if, perhaps, there is a problem with this mode (not working with those c674x) ?

  • Ludovic,

    Can you confirm that the TOUT pin is solely used for the Timer peripheral, since it is pinmuxed with I2C0, there is a chance that you might have external pulls on those lines which the 4clk Pulsewidth might not be able to oppose.  Just checking.  I've verified with our internal test team and its been verified to be functional in our product testing.  So it is sort of strange, Can you also verify that the internal pull ups/downs on the group of pins that the Timer is on are not driving?  The clk mode is likely able to drive properly as it stays driven by the timer module for a 50% duty cycle (longer than a small 4 clk pulse) but anyhow.  If you are able to send us a snapshot of the portion of the schematic that shows the timer output signal connections it could help.

    regards,

    miguel

     

  • Hi,

    Thanks for your help !

    The external connection of the TM64P2_OUT12 pin is very simple in our design, we have :

    DSP output (TM64P2_OUT12) --> serial resistor of 22 Ohm --> MAX11046 (CONVST pin, maxim adc)  ;  i/o of dsp are configured to support 3.3V

    We have no external pull up or pull down. PINMUX4 = 0x22221488, which means that TM64P2_OUT12 functionnality drives pin G16.

    I try to disable internal pull up / down (PUPDENA=0xfffff7ff) : no changes (ok in clock mode, nok in pulse mode, i tried 32 unchained mode, 32 chained mode and 64 bit mode). I put our scope (time base 2ns) directly on TM64P2_OUT12 (before the serial resistor), and in pulse mode i can't see any pulses or any starting of any pulses, i think that i should see a little variation of the output if i had a problem with a pull up/down resistor.

    - I need a precision : when in chained mode, PWID12=3, and TM64P2_OUT12 configured in pulse mode (supposed to be ok), the output width is :

    1) 4 clock of input clock of the timer (150MHz)

    2) or 4 clock of input clock of timer 12 (which is 150MHz divided by prescaler value (PRD34))

    - Is it possible to find a tested example (timer in pulse mode) that i can test on our board ?