Other Parts Discussed in Thread: AM69A
Hi
I am designing a board with AM69A but I want to learn about PCIe ref clock outputs.
My PCIe connections as below.
PCIe0 >>4 lane to VPX conn
PCIe3 >>2 lane to VPX conn
PCIe1>> 2 lane to M.2 connector.
I want learn that can I use serdes ref clock outputs for each PCI's. In sprz536a document TI doesn't suggest using ref clock output for 4 lane GEN3 connection?
Is there any update?
Thank you.
