Address alignment control of SRIO for read by other processor

Yariv,

I'm not 100% certain I understand exactly what you're saying is happening so can you verify my understanding and correct it as needed?

It sounds like you're saying the DSP (writes) -> FPGA via EMIF  then DSP (reads) <- FPGA via SRIO (NREAD) and the resulting SRIO NREADS land 64bit aligned (doesn't matter if read address is at when address of read is at 0xXXXX XXX0/4 it pulls from 0xXXXX XXX0 and for 0xXXXX XXX8/C it pulls from 0xXXXX XXX8.

Have you tried reading back from EMIF to verify that the locations are correct?  Also can you try doing a SRIO write from FPGA to see if it's consistent.

I'll ask someone else w/ more SRIO experience to follow up, but I think it should pull the data from an NREAD w/o concerns for data alignment (which would be handled by FPGA in this case.)

Best Regards,

Chad

The SRIO standard dictates that packets are sent with 3 lsb's of the address = 0 (double word, 8B aligned).  SRIO uses wrsize and wrptr to access non-double word aligned addresses.  TI's SRIO peripheral will create the outbound packet address and wrsize/wrptr for you based on the address and payload size you program into the LSU registers.  Some combinations are illegal, here is the chart for what is legal:

Anything that straddles a double word aligned boundary takes a minimum of two RapidIO packets to be sent.  You want to avoid that for throughput and latency reasons.  So, if you specify LSU Byte_count as 4B, the RapidIO_address[2:0] should be set to either 000, or 100 depending on which half of the double word you want to access.  I'm a little confused also on what you are seeing, but if you are doing the above correctly, then I would say your access issue is endian related assuming you are operating in little endian on the DSP.  You would either have to change the byte swapping boundary scheme the DSP is using, or adjust your addressing scheme used for the LSU transactions.

Regards,

Travis

Chad,

Thanks for the response (first time I'm responded :) ).

The correct decsription of our setup is :  DSP(writes)-> FPGA via EMIF, an address (32 bit)  from which FPGA should read via SRIO.

Then FPGA(reads) <- DSP via SRIO (amount of 256 bytes) . What we see is that reading are 64bit aligned (i.e. FPGA read same first word  in case three lsb address are 100 or 000).

(I assume that you'd involved Travis in that issue so I will answer him as well)

Thanks a lot

Yariv

Travis ,

Thanks a lot for the detailed response.

It was something that wasn't clear to me when reading TMS320C6457 DSP SRIO manual (SPRUGK4D.pdf), I'd always assumed by mistake that only 2 lsb's should be cleared. We'll deal with the 64 bit alignment within our application (3 lsb's of address will be cleared when provided to SRIO for NREAD request, byte count and first word to process will be updated in case original address 3 lsb's=4B).

Completing the description for what wasn't understood. The results which we'd reported were observed were after we did configure the endian conversion to D mode (swap on 8 byte boundary) .

As I didn't see this limitation on address and byte length limitation. My last question will be how DSP's SRIO module will react on such illegal combination (would it be reflected in any status register?) .

Best regards

Yariv