AM6526: SysFW v1.0 vs v2.1, different issues.

Also, wish in the PDK, you would separate board specific settings from the general libraries, or processor general source.  I.E. in the K3 DDR config, you have a output used to enable/disable the VTT regulator, which causes conflict with our design. (I always have VTT turned on, so I could comment it out.)  Also items dealing with the SDCard driver and Uart ports.  It just makes it hard to even able to compile a simple app, that would run on the EVM/IDK and our board.

Just a little side note.

Hi Robert Morse

Thanks for your query.

Which SDK you are working on ?

Regards

Ashwani

Using version pdk_am65xx_09_01_002

Little follow-up, running the pm_baremetal_clkrate_testapp, using mcu1_0 or mcu1_1 passes the tests. 

Running the pm_baremetal_systemconfig_testapp_mcu1_0, stops at "TISCI_DEV_COMPUTE_CLUSTER_CPAC_PBIST0: " it prints a "P" and stops.  It stops when running the mcu1_0 or mcu1_1.

Going back a little, and trying to figure out why sysfw_sr1 allows the DDR4 memory to initialize and setup. But sysfw_sr2 locks up waiting (Spin loop waiting for bit 1 of CSL_EMIF_PHYCFG_PGSR0 to be set) for PHY_Init() to complete. (A 0x73 is input to DDRPHY_PIR Register : (PHYRST|DCAL|PLLINIT|ZCAL|INIT).  Anything that is different between sr1 and sr2 in terms of DDR memory?

Some logs of boot from SR1 to SR2

Log of initializing DDR Memory

-----------------------------------------------------------
Using SYSFW_sr1:
SBL Revision: 01.00.10.01 (Apr  8 2024 - 08:19:10)
SBL_SciClientInit()
SBL_ReadSysfwImage(&sysfw_ptr, 270336)
MMCSD_socGetInitCfg: 0:/sysfw.bin
MMCSD_socSetInitCfg(0,&hwAttrsConfig)
FATFS_Init()
FATFS_open(0U, NULL, &sbl_fatfsHandle)
f_open(&fp, 0:/sysfw.bin, ((BYTE)FA_READ)
SYSFW  ver: 22.1.1--v2022.01 (Terrific Llam
Sciclient_setBoardConfigHeader... PASSED
Board_init(BOARD_INIT_PINMUX_CONFIG)
Sciclient_configPrmsInit()
Sciclient_init()
SBL_SocLateInit()
Initlialzing PLLs ...done.
InitlialzingClocks ...done.
Initlialzing DDR ...
        DDR Controller PHY Config...
        DDR4...
        PHY_Init()... 00000000
                 Calibration Started
                 REG = 8000000f
        SDRAM_Init()...
        WriteLeveling_Training()...
        DQSGate_Training()...
        WriteLevelAdjustment()...
        Training2()...
        VREF_Training()...
        Cleanup_Training()...
*****************DDR INIT OK******************
done.
Initializing GTC ...Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...

------------------------------------------------------------
Using SYSFW_sr2:
SBL Revision: 01.00.10.01 (Apr  8 2024 - 08:19:10)
SBL_SciClientInit()
SBL_ReadSysfwImage(&sysfw_ptr, 270336)
MMCSD_socGetInitCfg: 0:/sysfw.bin
MMCSD_socSetInitCfg(0,&hwAttrsConfig)
FATFS_Init()
FATFS_open(0U, NULL, &sbl_fatfsHandle)
f_open(&fp, 0:/sysfw.bin, ((BYTE)FA_READ)
SYSFW  ver: 22.1.1--v2022.01 (Terrific Llam
Sciclient_setBoardConfigHeader... PASSED
Board_init(BOARD_INIT_PINMUX_CONFIG)
Sciclient_configPrmsInit()
Sciclient_init()
SBL_SocLateInit()
Initlialzing PLLs ...done.
InitlialzingClocks ...done.
Initlialzing DDR ...
        DDR Controller PHY Config...
        DDR4...
        PHY_Init()... 00000000

-- Does not even look like it is getting past the HW_WR_DDRPHY_REG32(CSL_EMIF_PHYCFG_PIR, 0x73);
-- as it does not print out the "Calibration Started" message

-------------------------------------------------------------
PHY_Init() code: (Modified for more debugging)

static void PHY_Init()
{
    uint32_t cnt = 0;
    uint32_t reg;

    UART_printf("\tPHY_Init()... %08x\n",HW_RD_DDRPHY_REG32(CSL_EMIF_PHYCFG_PGSR0));
    /* PHY Initialization Register - kicks off init */
    HW_WR_DDRPHY_REG32(CSL_EMIF_PHYCFG_PIR, 0x73);

    UART_printf("\t\t Calibration Started\n");

    /* must wait 10 clock cycles before polling for init done */
    boardDDRDelay();
    boardDDRDelay();
    boardDDRDelay();
    boardDDRDelay();

    /* wait for PGSR0.IDONE */
    do {
        reg = HW_RD_DDRPHY_REG32(CSL_EMIF_PHYCFG_PGSR0);
        if ((cnt++ % 100) == 0) UART_printf("\t\t REG = %08x\n", reg);
    } while ((reg & 0x1U) != 0x1U);
        
    /* wait another 32 ctl_clk cycles before resuming further traffic */
    boardDDRDelay();
    boardDDRDelay();
    boardDDRDelay();
}

----------------------------------------------------------

Am at a loss of what to look for.

Still waiting for any kind of insight on why, I can initialize the DDR4 memory with sysfw_sr1.bin and stops dead with sysfw_sr2.bin. I understand it might be a board issue, or some configuration in the tiboot3.bin file that is made. As it is hard to determine what needs to be changed in the PDK to handle a custom board from the evm/idk.

Robert

Robert

I am afraid the support for this device is very limited and the PDK is no longer supported. 

Is this a new design or you running into issues with an existing design?

Regards

Mukul

It was for a new design, Just got the prototype back and this is what I am trying to bring up.  Originally using the evm for some development, and was happy with it, using I think version 6 of the pdk stuff.  Not looking for a processor that runs linux, need a high performance CPU that will run an embedded RTOS. If TI is not going to fully support the am65xx, let me know as I'll have to look for another processor, and I think TI will be dropped to the bottom of the list. 

Hello Robert

I would absolutely not encourage you to use this processor for non Linux development. We have deprecated the PDK and have a limited functionality MCU+ SDK and then remainder of features are predominantly for Linux developers. We also do not offer any safety software or secure boot for non linux users. 

The SDK now also has a note highlighting that this device software is now in bug fix only mode and no new features and enhancements are planned

If you need a non Linux processor , i recommend looking at AM243, if you need a non display/GPU processor with Linux and reasonably decent amount of RTOS foot print, you can look at AM64 family of devices. 

I have pinged a few folks in case they have any pointers on your specific problem, but again if this is beginning of your software development journey and you want this to be predominantly non Linux, this will be a very difficult development path. 

Regards

Mukul 

Additionally if the product requires RTOS , and you may want to also evaluate Windriver/VxWorks, they do have robust BSPs available for this device. 

Ok, but still trying to find the original issue.  What is the difference between sysfw_sr1 and sysfw_r2, as sysfw_sr1 I can get past the DDR configuration but with sysfw_sr2 I can not. As even going the linux route, I think sysfw is still used, though I don't know if the DDR Configuration is not done, until uboot is loaded.

You will need to use sysfw_r2 with silicon revision 2. If you are not seeing this work with SR2.0 silicon you may have a board/DDR configuration problem somewhere.