AM6421: GPMC interface: Maximum NAND Flash support

Hello Sandeep,

In AM64X, NAND device is interfaced to GPMC in 8 bit address and data multiplexed .

In this mode, it 4 CS lines each one can be support till 128M bytes and total 1GBytes .

And recently we had discussion with Hw Engineer to support parallel connection for NAND or NOR devices he has given below suggestions .

133MHz requires very tight timing closure, made worse with slow rise/fall times with 4 capacitive loads. A simulation may be required to check setup/hold times. We’d want the memories all placed very close to SOC. Branching of signals will cause reflections which need to settle before being considered stable for setup time. You  can run a quick IBIS sim to show these effects.

So, better don't go with parallel connection .

Sandeep NS said:

AM64x ROM only supports boot from ONFI 1.0 compatible 8 bit parallel NAND memory up to 2Gbytes in size

How did it get to 2GB  ? I need to confirm with other experts on this.

Sandeep NS said:

Thus, I got confused by this as to whether I should be using NAND flash for anything other than booting, as 128MB (1Gb) is the largest NAND flash that AM6421 can support as a single chip.?

Yes, maximum 128 M Bytes NAND chip can only support the GPMC interface.

Actually , there is no issues  if you want to use the NAND memory in Application other than booting . For booting, you can go with  the OSPI or emmc or SD interface .

Regards,

S.Anil.

Hello Sandeep,

Please don't consider above points .

I got confused between NAND and NOR memories.

Whatever information is shared seems wrong, and it is not applicable to NAND memories. Sorry for that.

Please look at the below NAND interface diagram.

We need 8 data lines and other control signals.

As per TRM, we support a maximum of 1 GB of NAND memory.

So, you can connect 1GB NAND memory to GPMC .

Typically, for NAND memory, the memory array has pages and blocks.

Each page has 2 KBytes, 4 KBytes, or X KBytes based on your NAND memory selection.

Block size is a combination of pages; for example, 1 block size equals 52 pages or x pages based on NAND memory.

So, here, if you want to read or write data from NAND memory, you can read the data in the form of pages.

So,you don't need to worry about how much CS size should be configured in the real-time application for NAND memories.

The CS size should be your page size. So, you can configure CS size to any value from 16 MB to 256 MB; there are no issues.

I hope I have cleared your two queries, and for the third query, give me some time by today to see how we can support 2GB in ONFI mode.

Please let me know if you still have any queries .

Regards,

S.Anil.

Hello Sandeep,

I discussed with the internal team for what the maximum size of NAND memory can be connected to the GPMC ?

In our discussion, we have concluded that there is no size restriction of an NAND device. So, you can connect to 1Gbytes or higher sizes.

You can go ahead with the high range of NAND memory with CS 0 and there are no issues.

Actually, this NAND device memory is not mapped to the SOC address. So, whatever mentioned CS size in TRM i.e. 16 Mbytes to 256 Mbytes is not valid for NAND memories and valid to NOR and PSRAM memories.

And there is one more query related to ONFI flash,

The 2Gbytes limit is set in the ROM code. Higher capacity devices will not work to boot from.

Regards,

S.Anil.