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How much liberty does TI have from ARM?

Anonymous
Anonymous
Guru 17045 points
Other Parts Discussed in Thread: AM1808, AM1802

Hi,

 

I would like to ask a question on AM18x processors. The attached diagram is from SPRS653A, AM1808 ARM Microprocessor.

 

 

I have compared Peripherals (I2C, EDMA, MSASP, LCDc, VPIF) feature and usage with other TI devices not in the ARM family (OMAP, DaVinci, MPU) and found that these peripherals are almost the same. This means that AM18x and AM18x uses the same peripheral design as other devices.

 

On the other hand, AM18x uses ARM926EJ-S RISC core, which is different from devices that I compared with above. So schematically, does AM18x consisting of two parts:

1.    Core: ARM926EJ-S

2.    Peripherals: same as other TI devices

?

 

Is this understanding correct?

 

And for the part I enclosed in green circle, is it 100% prescribed in ARM926EJ-S standard? It makes sense that the instruction set must be fully ARM926EJ-S compatible, but does TI add instruction set extension to that? Does ARM allowed licensed manufacturers to add their own instruction extensions?

 

 

And regarding L1, L2 cache and memory size, is it fully specified in ARM standards? Does ARM allow manufacturer to determine it themselves? It seems to me reasonable, and I have found that AM1802 has less L2 cache than other devices which is a counterexample if on-chip memory/cache sizes are fully prescribed by ARM; or does ARM prescribe a range (like 32KB~256KB) in this case?

 

I am new to ARM. Hope someone could explain these questions.

 

 

 

 

Zheng

 

 

  • 0
    TI__Intellectual 2620 points

    Zheng,

    In the green box you showed, there are several sub modules. Only the box labled "ARM926EJS CPU with MMU" would correspond to what you referred to as "Core: ARM926EJ-S". This sub-module is completely ARM compatible as described in the ARM926EJS TRM from ARM Ltd. TI does not add any extension to this ISA. There are "ARM-core related" supporting blocks such as cache, vector table, rom, ram, embedded trace that may be licensed from ARM IP library, but from a SW standpoint they are generic.

    The other modules/ peripherals listed (memories, debug/ trace, I/Os, etc...) are additional system IPs that are shared with various other TI devices as you noted. This includes the "system control" and JTAG interface blocks inside the green rectangle that you drew.

  • Anonymous
    0 Anonymous in reply to Loc Truong
    Guru 17045 points

    Loc,

    Great answer, it resolved my questions.

    Loc said:

    There are "ARM-core related" supporting blocks such as cache, vector table, rom, ram, embedded trace that may be licensed from ARM IP library, but from a SW standpoint they are generic.


    What do you mean that they might be licensed from ARM IP library? Could you elaborate more on this?

      
    Zheng

  • 0 in reply to Anonymous
    TI__Intellectual 2620 points

    ARM Ltd also licenses additional IPs as part of their offering. For more nfo see http://www.arm.com/products/system-ip/index.php 

  • Anonymous
    0 Anonymous in reply to Loc Truong
    Guru 17045 points

    I got it, thanks.

     

    Zheng