AM625: AM625 detailed docs for R5F?

hello David Alessio

Thank you for the query.

You might have to refer to the ARM documentation if you are looking for R5F documentation.

Please add additional details on your requirements if that is not the case.

Regards,'

Sreenivasa

Hello, Sreenivasa,

Thank you for your prompt reply.  We're not new to the R5F.  What I'm asking for are the implementation specifics, where is its memory mapped to?  What are the SoC controls registers that halt it, or release it?  Which interrupts can be steered to the R5F?  This info is SoC specific and is not to be found in the ARM docs.  Please advise.

Regards,

-david

hello David Alessio

Thank you and good to note your familiarity.

David Alessio said:

Reviewing the docs for the AM62x, I can see a few references to a Cortex R5F, changes to its max clk, etc.  Where can I find detailed documentation on it?  It's configuration, TCM if any, bus access, access to external pins, if any, etc.?

I assume you are using the latest TRM,

Please refer below section and do let me know if this helps.

4.2.2 Arm Cortex R5F Subsystem (WKUP_R5FSS)
7.2 Device Manager Cortex R5F Subsystem (WKUP_R5FSS)
10.1.9 Interrupt Connections for R5FSS

Regards,

Sreenivasa

Hello David Alessio

Below are some additional references

https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/09_02_00_38/exports/docs/api_guide_am62x/DEVELOP_AND_DEBUG_DMR5.html

This is generic guide. Apart from this, most of the examples are available on R5 also:
https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/09_02_00_38/exports/docs/api_guide_am62x/EXAMPLES_HELLO_WORLD.html

"CPU+OS" in the 'Supported Combinations' table

Regards,

Sreenivasa