IDMA for Memory Exchange Question

demon popo

Intellectual 625 points

Hello,

I'm using IDMA for C6670 memory exchange, but it have some problem, memory can't use IDMA transport

Could someone help figuring out why IDMA does not work, or how to use DDR3 transport?

CSS Version: 5.0.3

Best Regards,

===================================================================================================================

void EDMA_Transport()

{

unsigned int pp1[255];

unsigned int pp2[255];

int i;

for(i=0;i<255;i++)

{

pp1[i]=0x01110000;

}

L1P_CFG = 0x00; //no cache

L1D_CFG = 0x00; //no cache

L2_CFG = 0x00; //no cache

L1P_INV = 0x00;

L2_INV = 0x00;

IDMA0_MASK = 0x4F4F4F4F; //Set mask for 8 regs -- 11:8, 3:0

IDMA0_SOURCE = *pp1; //Set source to config location

IDMA0_DEST = *pp2; //Set destination to data memory address

IDMA0_STAT = 0x01;

IDMA0_COUNT = 0x00000001; //Set mask for 1 block

while (IDMA0_STAT); //Wait for transfer completion ... update register values ...

IDMA0_MASK = 0x4F4F4F4F; //Set mask for 8 regs -- 11:8, 3:0

IDMA0_SOURCE = *pp2; //Set source to updated value pointer

IDMA0_DEST = *pp1; //Set destination to config location

IDMA0_COUNT = 0x00000001; //Set mask for 1 block

printf("IDMA0_SOURCE = %x\n",IDMA0_SOURCE);

printf("IDMA0_DEST = %x\n",IDMA0_DEST);

}

over 14 years ago

0 RandyP over 14 years ago

TI__Guru* 84110 points

Please re-read the IDMA section of the CorePac User's Guide SPRUGW0. It explains the features and limitations of the IDMA0 and IDMA1 commands. I do not believe I can explain it better than the User's Guide does.

IDMA0 and IDMA1 are not replacements for QDMA or other EDMA3 controllers. You may also want to read the comments on the code that you copied from that section to make your test case, above. For example,

demon popo said:
IDMA0_SOURCE = *pp1; //Set source to config location

First, this is not what you meant to write. *pp1 reads the content of the first element of the pp1 array and this instruction writes that value to the source address register. You meant to put pp1 or &pp1[0]. The way you wrote it, the IDMA0_SOURCE register would be set to 0x01110000.

Second, the comment says this should be a config location. But it is not. It is a memory address on the stack or wherever aggregate data is placed. If this is supposed to be DDR memory, re-read section 5.1.1 to see the list of addresses that can be used. If you go outside of those memories, then this will not work.

Regards,
RandyP

If you need more help, please reply back. If this answers the question, please click Verify Answer , below.

Processors

Processors forum

IDMA for Memory Exchange Question