how many the decoder ..?

Coding_ farmer

Other Parts Discussed in Thread: TVP5158

SDK the latest one;

Does the DM8168 have 4 channels of video inputs?

i change some thing that the DM8168 can decode 4 HD channels

but also just can decode 4 channels of D1 ,when i create 5 decoders ,it is Success.but when i set the 5th decoder from loaded status to idle status,

it failed.the 5th can get the event when the idle set Success.

but According to Michael Risley that The 8168 can simultaneously enc/dec three HD channels (or even 30 channels of D1).

Does the DM8168 have 4 channels of video inputs?can't decode more?

over 14 years ago

0 Vimal Jain over 14 years ago

TI__Expert 6535 points

DM8168 can have more than 4 channels input. For example if board supports video encoder chip TVP5158, it can capture 16 D1 signals.

For creating more than 4 channels of decode, may be you are running short of memory allocated by default. You can see the media controller logs

by doing /usr/share/ti/ti-uia/loggerSMDump.out 0x9e400000 video.

For changing memory following link can be used;

http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map

0 Coding_ farmer over 14 years ago in reply to Vimal Jain

Prodigy 50 points

Thanks Vimal,

I change the meory map( MC_HDVICP2_INT_HEAP_CACHED & IPC_SR_FRAME_BUFFERS ) by http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map

,Then, Can decode 4 HD channels & run without any err,but when i create the fifth decoder,it can create,but, setting the decoder to idle state and alloc the input & output buffers,it failed.( No matter how much memory I allocated )

Use system_top Command output:

sys_top Ver : 0.2.0.0
Number Of Running Cores: 3

DSP :
Not Running or Do not integrate sys_top functionality

MC.HDVICP2:
0 Heap:Size 1048576    Used 567048     MaxU 567048     Free 481528     LarF 481192
Num SR :4
SRIn 0 :PhyA 0x9f700000 Virt 0x0        Size 0x200000
SRHeap:Size 2095488    Used 19840      MaxU 19840      Free 2075648    LarF 2075648
SRIn 1 :PhyA 0x9a100000 Virt 0x0        Size 0x100000
SRHeap:Size 1048448    Used 0          MaxU 0          Free 1048448    LarF 1048448
SRIn 2 :PhyA 0x9f900000 Virt 0x0        Size 0x10000000
SRHeap:Size 268435328 Used 8559360    MaxU 8559360    Free 259875968 LarF 259875968

MC.HDVPSS:
0 Heap:Size 2097152    Used 107568     MaxU 107568     Free 1989584    LarF 1989584
1 Heap:Size 28311552   Used 0          MaxU 0          Free 28311552   LarF 28311552
Num SR :4
SRIn 0 :PhyA 0x9f700000 Virt 0x0        Size 0x200000
SRHeap:Size 2095488    Used 19840      MaxU 19840      Free 2075648    LarF 2075648
SRIn 1 :PhyA 0x9a100000 Virt 0x0        Size 0x100000
SRHeap:Size 1048448    Used 0          MaxU 0          Free 1048448    LarF 1048448
SRIn 2 :PhyA 0x9f900000 Virt 0x0        Size 0x10000000
SRHeap:Size 268435328 Used 8559360    MaxU 8559360    Free 259875968 LarF 259875968

/usr/share/ti/ti-uia/loggerSMDump.out 0x9e400000 video output:

N:Video P:1 #:00831 T:00000024|9bd07869 S:Entered: OMX_BASE_DIO_Init (0x9da21d10, 1, OMX.DIO.NONTUNNEL, 0x9da2168c)
N:Video P:1 #:00832 T:00000024|9bd11ab5 S:Module<OMX.TI.DUCATI.VIDDEC> Leaving<OMX_BASE_DIO_Init> @line<172> with error<0:ErrorNone>
N:Video P:1 #:00833 T:00000024|9bd17b25 S:Module<OMX.TI.DUCATI.VIDDEC> Entering<OMX_BASE_DIO_Open> @line<252>
N:Video P:1 #:00834 T:00000024|9be04f5f S:Module<OMX.TI.DUCATI.VIDDEC> Leaving<OMX_BASE_DIO_Open> @line<257> with error<0:ErrorNone>
N:Video P:1 #:00835 T:00000024|9be1bbbd S:OMX_TI_VIDDEC_CommandNotify::Line 2118::VDEC Error->VIDDEC3_create Failed
N:Video P:1 #:00836 T:00000024|9be2ee77 S:Entered Function :omxrpc_skel_allocbuffer
N:Video P:1 #:00837 T:00000024|9be6318b S:Entered Function :omxrpc_skel_allocbuffer
N:Video P:1 #:00838 T:00000024|9be94dd9 S:Entered Function :omxrpc_skel_allocbuffer
N:Video P:1 #:00839 T:00000024|9bec7119 S:Entered Function :omxrpc_skel_allocbuffer
N:Video P:1 #:00840 T:00000024|9bf08669 S:Module<OMX.TI.DUCATI.VIDDEC> Leaving<OMX_BASE_PROCESS_CmdEvent> @line<786> with error<-2147479552:ErrorInsufficientResources>
N:Video P:1 #:00841 T:00000024|9bf10d3d S:Module<OMX.TI.DUCATI.VIDDEC> Leaving<OMX_BASE_CmdEventHandler> @line<468> with error<-2147479552:ErrorInsufficientResources>
N:Video P:1 #:00842 T:00000024|9bf1896f S:Module<OMX.TI.DUCATI.VIDDEC> Entering<OMX_BASE_CmdEventHandler> @line<437>
N:Video P:1 #:00843 T:00000024|9bf1e5ff S:Module<OMX.TI.DUCATI.VIDDEC> Leaving<OMX_BASE_CmdEventHandler> @line<468> with error<0:ErrorNone>

Setting error?Can anyone tell me how to set it? Thanx;

0 Vimal Jain over 14 years ago in reply to Coding_ farmer

TI__Expert 6535 points

Are you trying HD channels or smaller resololution. Could you please try say CIF or QCIF resolution to test if you can create > 4 channels. Most likely it should be heap running out of memory.

Regards

Vimal

0 Coding_ farmer over 14 years ago in reply to Vimal Jain

Prodigy 50 points

According to your reply, I tried create 5 CIF (also QCIF)channels to test ,There is still the same problem. Can't set decoders to idle state.

But the same Program, running under ezsdk5_01_01_80,can create 5 CIF channels and runing without any err,but this SDKjust allow me to create only one HD channel(>1 will failed).

Are there examples that Successfully decoding multiple-channlel video ?

Thanks

0 Vimal Jain over 14 years ago in reply to Coding_ farmer

TI__Expert 6535 points

As per your earlier post "Can decode 4 HD channels & run without any err"

so It confuses now, when you say > 1 will fail. We have tried 2 HD decoder, and some community members have also tried 2 HD decode and that works. we will check for >4 D1 decoders.

Regards

Vimal

0 Coding_ farmer over 14 years ago in reply to Vimal Jain

Prodigy 50 points

I'm sorry for my bad expression. It can decoding 4 HD channels(also 4 D1 channels,but more will fail) by using ezsdk5_02_01_59,

can decoding 1 HD channel( 5 D1 channels) by using ezsdk5_01_01_80.

Thanx

Processors

Processors forum

how many the decoder ..?