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SATA Near-end Analog Loopback

Other Parts Discussed in Thread: OMAP-L138

Hi,

I'm currently working on some functions checking the status of the used hardware-interfaces. I already achieved to spin an attached SSD up, read and write one sector and to execute DEVICE DIAGNOSTIC and IDENTIFY DEVICE. This is sufficient for me in any cases a device is attached to the SATA-port.

Additionally it is also necessary to check the SATA interface without the need of any SATA-device attached to the port. So for this hardware test I detach the SSD, ran some hardware inits (pinmuxConfig, GIOP_setDir, GPIO_setOutput, pllInit, setFocedmode, enable_LPSC_SATACLK, power_LJCB_RCD) and tried to set the NEALB bit of the BISTCR register. But unfortunately I can change any element of BISTCR without NEALB (NEALB simply doesn’t change from ‘0’ -> ‘1’). I already tried to put the device to the SLUMBER / PARTIAL mode before writing NEALB but this was also useless. Is there any additional condition which protects the NEALB bit? What do I have to do so that I can set the NEALB bit respectively performing a near-end analog loopback?

Further information:

I use the LOGICPD board wit OMAP-L138
the CCS5 Version: 5.1.0.07001
and the XDS100 Ver 2.0

The code of the the hardware-inits befor writing to NEALB:
   // clear the buffer enable to start the sata clock.
   EVMOMAPL138_pinmuxConfig(PINMUX_GPIO_BUFF_OE_REG, PINMUX_GPIO_BUFF_OE_MASK, PINMUX_GPIO_BUFF_OE_VAL);
   GPIO_setDir(GPIO_BUFF_OE_BANK, GPIO_BUFF_OE_PIN, GPIO_OUTPUT);
   GPIO_setOutput(GPIO_BUFF_OE_BANK, GPIO_BUFF_OE_PIN, OUTPUT_LOW);

   //Used by DV only and doing PLL initalization
   pllInit();

   // setting  force mode to bypass clock acknowledge from module
   pscRegs->MDCTL[LPSC_SATA] |= CSL_PSC_MDCTL_FORCE_MASK;

   //Enable the LPSC
   //Enable SATA Clk
   EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_SATA, PSC_ENABLE);

   // powerup LJCB & RCD modules
   *(Uint32 *)SATACLK_PWRDN=0x0;

 

Thanks in advance

Stefan Hittmeyer