Other Parts Discussed in Thread: AM1808
Hi,
I would like to ask a question on AM1808 cache.
According to Features, p.1, spru653a AM1808 ARM Microprocessor, AM1808 has
Can both instruction and data cache be configured as L1 RAM? On DaVinci products, for example DM6437, both L1 and L2 allow flexible allocation. Is this possible with AM1808?
Zheng
