Other Parts Discussed in Thread: TPS65220, SK-AM64B
Hello i would like to better understand what it is mandatory for having Boot over ethernet supported on AM64x cpu if we are using PMIC TPS65220 and 2xPHY DP83822 with RMII config on same MDIO bus.
I understand that PHY should be power-up and out of reset before the BOOTROM code execution.
I also understand that only boot over RMII2 connect to CPSW3G is supported (following Table 4-24. RMII Pin Usage).
We have configured the BOOTMODE pins to support boot over Ethernet on the secondary boot option. (B10 = 0, B11 = 0, B12 = 1, B13 = 1 (RMII with external clock source))
What is not clear for me is the MDIO phy scan sequence. Inside the AM64x TRV manual, info given is:
"4.4.5.1.1 Ethernet Initialization Process"
When Link Info = 0, the link parameters are read using MDIO scan. This is the typical setting when using an
external PHY. When Link Info = 1, no MDIO scan is performed, and the link parameters are programmed by the
ROM based on the RGMII status register.
I have try to look the SK-AM64B schematic board and my understand is that we will be in same situation on my custom board schematics, when ROMBOOT will execute its Ethernet initialization process, the both PHY are power-up and out of reset and are on the same MDIO bus.
So how the ROMBOOT know which PHY address to use on the MDIO Bus ?
Thanks in advance for the clarification.
