I'm bolting up an FPGA to the GPMC bus. For good reason, I'd like to have the FPGA's clock signal be continuous.
The GPMC_CLK is driven by GPMC_FCLK, which is in turn driven by the L3 interface clock. Can I use another peripheral's clock, continuously running and divided down appropriately, to source my FPGA and still be synchronous with GPMC_CLK?
Thanks in advance.