AM625: console output UART0 to UART2

sivakumar parames

Part Number: AM625

HI,

I have a custom board based on AM625 and needed to get console output in UART2. I tried this following patch specified in below thread. Basically I get few lines output. After that it stops. Please let me know what would be the probable issue?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1295252/am623-changing-console-from-uart0-to-uart2/4916153#4916153

output from UART-2:

U-Boot SPL 2021.01-g2ee8efd654 (Feb 24 2023 - 05:36:12 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.4--v08.06.04 (Chill Ca2c)

k3_ddrss memorycontroller@f300000: clk get failed-2

the following patch has been applied.

diff --git a/arch/arm/dts/k3-am62x-r5-sk-common.dtsi b/arch/arm/dts/k3-am62x-r5-sk-common.dtsi
index b4a5e3cfa1..d5976095e9 100644
--- a/arch/arm/dts/k3-am62x-r5-sk-common.dtsi
+++ b/arch/arm/dts/k3-am62x-r5-sk-common.dtsi
@@ -13,7 +13,7 @@
 	};
 
 	chosen {
-		stdout-path = "serial2:115200n8";
+		stdout-path = "serial4:115200n8";
 		tick-timer = &timer1;
 	};
 
diff --git a/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi b/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi
index b57d9563d8..acc064337a 100644
--- a/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62x-sk-common-u-boot.dtsi
@@ -6,7 +6,7 @@
 
 / {
 	chosen {
-		stdout-path = "serial2:115200n8";
+		stdout-path = "serial4:115200n8";
 		tick-timer = &timer1;
 	};
 
diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi
index 72ebb1400f..58a3bc713e 100644
--- a/arch/arm/dts/k3-am62x-sk-common.dtsi
+++ b/arch/arm/dts/k3-am62x-sk-common.dtsi
@@ -14,7 +14,7 @@
 
 / {
 	aliases {
-		serial2 = &main_uart0;
+		serial4 = &main_uart2;
 		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
 		mmc2 = &sdhci2;
@@ -25,8 +25,8 @@
 	};
 
 	chosen {
-		stdout-path = "serial2:115200n8";
-		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+		stdout-path = "serial4:115200n8";
+		bootargs = "console=ttyS4,115200n8 earlycon=ns16550a,mmio32,0x02820000";
 	};
 
 	memory@80000000 {
@@ -154,10 +154,17 @@
 };
 
 &main_pmx0 {
-	main_uart0_pins_default: main-uart0-pins-default {
+	// main_uart0_pins_default: main-uart0-pins-default {
+	// 	pinctrl-single,pins = <
+	// 		AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
+	// 		AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+	// 	>;
+	// };
+
+		main_uart2_pins_default: main-uart2-pins-default {
 		pinctrl-single,pins = <
-			AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
-			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+			AM62X_IOPAD(0x01d0, PIN_INPUT, 3) /* (B14) UART0_CTSn.UART2_RXD */
+			AM62X_IOPAD(0x01d4, PIN_OUTPUT, 3) /* (C13) UART0_RTSn.UART2_TXD */
 		>;
 	};
 
@@ -301,8 +308,7 @@
 };
 
 &main_uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart0_pins_default>;
+	status = "disabled";
 };
 
 &main_uart1 {
@@ -311,7 +317,9 @@
 };
 
 &main_uart2 {
-	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart2_pins_default>;
+	status = "okay";
 };
 
 &main_uart3 {

diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c
index 47ea973197..9f8d7d7e6f 100644
--- a/arch/arm/mach-k3/am62x/clk-data.c
+++ b/arch/arm/mach-k3/am62x/clk-data.c
@@ -115,11 +115,16 @@ static const char * const wkup_clksel_out0_parents[] = {
 	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
 };
 
-static const char * const main_usart0_fclk_sel_out0_parents[] = {
-	"usart_programmable_clock_divider_out0",
+static const char * const main_usart2_fclk_sel_out0_parents[] = {
+	"usart_programmable_clock_divider_out2",
 	"hsdiv4_16fft_main_1_hsdivout1_clk",
 };
 
+// static const char * const main_usart0_fclk_sel_out0_parents[] = {
+// 	"usart_programmable_clock_divider_out0",
+// 	"hsdiv4_16fft_main_1_hsdivout1_clk",
+// };
+
 static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
 	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
@@ -199,10 +204,12 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX("main_gpmc_fclk_sel_out0", main_gpmc_fclk_sel_out0_parents, 2, 0x108180, 0, 1, 0),
 	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
 	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
-	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
+	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108248, 0, 2, 0, 0, 48000000),
+	//CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
 	CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
 	CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
-	CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
+	CLK_MUX("main_usart2_fclk_sel_out0", main_usart2_fclk_sel_out0_parents, 2, 0x108288, 0, 1, 0), 
+	//CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), 
 	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
 	CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
 	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
@@ -297,10 +304,14 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
 	DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
 	DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
-	DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
-	DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
-	DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
-	DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	// DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
+	// DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
+	// DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
+	// DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(153, 0, "main_usart2_fclk_sel_out0"),
+	DEV_CLK(153, 1, "usart_programmable_clock_divider_out2"),
+	DEV_CLK(153, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
+	DEV_CLK(153, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(157, 20, "clkout0_ctrl_out0"),
 	DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
 	DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
diff --git a/arch/arm/mach-k3/am62x/dev-data.c b/arch/arm/mach-k3/am62x/dev-data.c
index f413313533..a1954d5ca2 100644
--- a/arch/arm/mach-k3/am62x/dev-data.c
+++ b/arch/arm/mach-k3/am62x/dev-data.c
@@ -62,7 +62,8 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(162, &soc_lpsc_list[10]),
 	PSC_DEV(75, &soc_lpsc_list[11]),
 	PSC_DEV(102, &soc_lpsc_list[12]),
-	PSC_DEV(146, &soc_lpsc_list[12]),
+	PSC_DEV(153, &soc_lpsc_list[12]),
+	// PSC_DEV(146, &soc_lpsc_list[12]),
 	PSC_DEV(13, &soc_lpsc_list[13]),
 	PSC_DEV(166, &soc_lpsc_list[14]),
 	PSC_DEV(135, &soc_lpsc_list[15]),

diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
index a598607ead..4f4c8bba1d 100644
--- a/include/environment/ti/boot.h
+++ b/include/environment/ti/boot.h
@@ -12,7 +12,8 @@
 #include <linux/stringify.h>
 
 #ifndef CONSOLEDEV
-#define CONSOLEDEV "ttyS2"
+// #define CONSOLEDEV "ttyS2"
+#define CONSOLEDEV "ttyS4"
 #endif
 
 #ifndef PARTS_DEFAULT

diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h
index 97bd7c1fd7..70004fbb79 100644
--- a/include/configs/am62x_evm.h
+++ b/include/configs/am62x_evm.h
@@ -129,9 +129,9 @@
                        "setenv name_fdt k3-am62x-lp-sk.dtb; fi;"       \
                "setenv fdtfile ${name_fdt}\0"                          \
        "name_kern=Image\0"                                             \
-       "console=ttyS2,115200n8\0"                                      \
+       "console=ttyS4,115200n8\0"                                      \
        "args_all=setenv optargs ${optargs} "                           \
-               "earlycon=ns16550a,mmio32,0x02800000 ${mtdparts}\0"     \
+               "earlycon=ns16550a,mmio32,0x02820000 ${mtdparts}\0"     \
        "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
 
 /* U-Boot MMC-specific configuration */

thanks,

siva.

over 1 year ago

0 Bin Liu over 1 year ago

TI__Guru**** 172861 points

Hi Siva,

sivakumar parames said:
k3_ddrss memorycontroller@f300000: clk get failed-2

It seems your clk related code change broke the DDR controller. I will review the details and get back to you next week.

0 sivakumar parames over 1 year ago in reply to Bin Liu

Prodigy 185 points

Hi Bin,

Any update?

thanks.

0 Bin Liu over 1 year ago in reply to sivakumar parames

TI__Guru**** 172861 points

Hi Siva,

Sorry for my late response. I will be looking at this tomorrow .

0 Bin Liu over 1 year ago

TI__Guru**** 172861 points

Hi Siva,

Please attach the file <SDK>/board-support/u-boot_build/r5/arch/arm/dts/k3-am625-r5-sk.dtb for me to review.

0 sivakumar parames over 1 year ago in reply to Bin Liu

Prodigy 185 points

Hi Bin, pls find relevant files.

Fullscreen 4331.k3-am62x-sk-common.txt Download

// SPDX-License-Identifier: GPL-2.0
/*
 * Common dtsi for AM62x SK and derivatives
 *
 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am625.dtsi"

/ {
	aliases {
		//serial2 = &main_uart0;
		serial4 = &main_uart2;
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
		mmc2 = &sdhci2;
		usb0 = &usb0;
		usb1 = &usb1;
		spi0 = &ospi0;
		remoteproc0 = &mcu_m4fss;
	};

	chosen {
		stdout-path = "serial4:115200n8";
		bootargs = "console=ttyS4,115200n8 earlycon=ns16550a,mmio32,0x02820000";
	};

	memory@80000000 {
		device_type = "memory";
		/* 2G RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;

	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9cb00000 0x00 0x100000>;
			no-map;
		};

		mcu_m4fss_memory_region: m4f-memory@9cc00000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9cc00000 0x00 0xe00000>;
			no-map;
		};

		secure_tfa_ddr: tfa@9e780000 {
			reg = <0x00 0x9e780000 0x00 0x80000>;
			alignment = <0x1000>;
			no-map;
		};

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
			alignment = <0x1000>;
			no-map;
		};

		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9db00000 0x00 0xc00000>;
			no-map;
		};
	};

	vmain_pd: regulator-0 {
		/* TPS65988 PD CONTROLLER OUTPUT */
		compatible = "regulator-fixed";
		regulator-name = "vmain_pd";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_5v0: regulator-1 {
		/* Output of LM34936 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vmain_pd>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_3v3_sys: regulator-2 {
		/* output of LM61460-Q1 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3_sys";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vmain_pd>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: fixed-regulator-sd {
		/* TPS22918DBVR */
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vcc_3v3_sys>;
		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
	};

	vdd_sd_dv: gpio-regulator-TLV71033 {
		/* Output of TLV71033 */
		compatible = "regulator-gpio";
		regulator-name = "tlv71033";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vcc_5v0>;
		gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&usr_led_pins_default>;

		led-0 {
			label = "am62-sk:green:heartbeat";
			gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
			function = LED_FUNCTION_HEARTBEAT;
			default-state = "off";
		};
	};

	extcon_usb0: extcon-usb0 {
		compatible = "linux,extcon-usb-gpio";
		id-gpios = <&main_gpio1 50 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&extcon_usb0_gpio_id_pins_default>;
	};
};

&main_pmx0 {
	main_uart0_pins_default: main-uart0-pins-default {
		pinctrl-single,pins = <
		AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
		>;
	};
	
	main_uart2_pins_default: main-uart2-pins-default {
		pinctrl-single,pins = <
		AM62X_IOPAD(0x05c, PIN_INPUT, 2) /* (D14) UART0_RXD */
			AM62X_IOPAD(0x060, PIN_OUTPUT, 2) /* (E14) UART0_TXD */
		>;
	};

	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
			AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
		>;
	};

	main_i2c1_pins_default: main-i2c1-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
			AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
		>;
	};

	main_i2c2_pins_default: main-i2c2-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
			AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
		>;
	};

	main_mmc0_pins_default: main-mmc0-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
			AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
			AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
			AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
			AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
			AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
			AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
			AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
			AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
			AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
		>;
	};

	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
			AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
			AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
			AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
			AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
			AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
			AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
		>;
	};

	usr_led_pins_default: usr-led-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
		>;
	};

	main_mdio1_pins_default: main-mdio1-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
			AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
		>;
	};

	main_rgmii1_pins_default: main-rgmii1-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
			AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
			AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
			AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
			AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
			AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
		>;
	};

	main_rgmii2_pins_default: main-rgmii2-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
			AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
			AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
			AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
			AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
			AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
		>;
	};

	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
		>;
	};

	extcon_usb0_gpio_id_pins_default: extcon-usb0-gpio-id-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x254, PIN_INPUT_PULLUP, 7) /* (C20) USB0_DRVVBUS.GPIO1_50 */
		>;
	};

	main_usb1_pins_default: main-usb1-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
		>;
	};

	ospi0_pins_default: ospi0-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
			AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
			AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
			AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
			AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
			AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
			AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
			AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
			AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
			AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
			AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
		>;
	};
};

&wkup_uart0 {
	/* WKUP UART0 is used by DM firmware */
	status = "reserved";
};

&mcu_uart0 {
	status = "disabled";
};

&main_uart0 {
//	pinctrl-names = "default";
//	pinctrl-0 = <&main_uart0_pins_default>;
	status = "disabled";
};

&main_uart1 {
	/* Main UART1 is used by TIFS firmware */
	status = "reserved";
};

&main_uart2 {
	status = "disabled";
};

&main_uart3 {
	status = "disabled";
};

&main_uart4 {
	status = "disabled";
};

&main_uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart2_pins_default>;
	status = "okay";
};

&main_uart6 {
	status = "disabled";
};

&mcu_i2c0 {
	status = "disabled";
};

&wkup_i2c0 {
	status = "disabled";
};

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;
};

&main_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <400000>;

	exp1: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
				   "PRU_DETECT", "MMC1_SD_EN",
				   "VPP_LDO_EN", "EXP_PS_3V3_En",
				   "EXP_PS_5V0_En", "EXP_HAT_DETECT",
				   "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
				   "UART1_FET_BUF_EN", "WL_LT_EN",
				   "GPIO_HDMI_RSTn", "CSI_GPIO1",
				   "CSI_GPIO2", "PRU_3V3_EN",
				   "HDMI_INTn", "TEST_GPIO2",
				   "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
				   "MCASP1_FET_SEL", "UART1_FET_SEL",
				   "TSINT#", "IO_EXP_TEST_LED";
	};
};

&main_i2c2 {
	status = "disabled";
};

&main_i2c3 {
	status = "disabled";
};

&sdhci0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc0_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&sdhci1 {
	/* SD/MMC */
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vdd_sd_dv>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&usbss0 {
	ti,vbus-divider;
};

&usb0 {
	extcon = <&extcon_usb0>;
};

&usb1 {
	dr_mode = "host";
	pinctrl-names = "default";
	pinctrl-0 = <&main_usb1_pins_default>;
};

&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mdio1_pins_default
		     &main_rgmii1_pins_default
		     &main_rgmii2_pins_default>;
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy0>;
};

&cpsw3g_mdio {
	cpsw3g_phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&mailbox0_cluster0 {
	mbox_m4_0: mbox-m4-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;
};

Fullscreen 8055.k3-am62x-sk-common-u-boot.txt Download

// SPDX-License-Identifier: GPL-2.0
/*
 * Common AM62x SK dts file for SPLs
 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/ {
	chosen {
		stdout-path = "serial4:115200n8";
		tick-timer = &timer1;
	};

	aliases {
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
	};

	memory@80000000 {
		u-boot,dm-spl;
	};
};

&cbass_main{
	u-boot,dm-spl;

	timer1: timer@2400000 {
		compatible = "ti,omap5430-timer";
		reg = <0x00 0x2400000 0x00 0x80>;
		ti,timer-alwon;
		clock-frequency = <25000000>;
		u-boot,dm-spl;
	};
};

&dmss {
	u-boot,dm-spl;
};

&secure_proxy_main {
	u-boot,dm-spl;
};

&dmsc {
	u-boot,dm-spl;
};

&k3_pds {
	u-boot,dm-spl;
};

&k3_clks {
	u-boot,dm-spl;
};

&k3_reset {
	u-boot,dm-spl;
};

&wkup_conf {
	u-boot,dm-spl;
};

&chipid {
	u-boot,dm-spl;
};

&main_pmx0 {
	u-boot,dm-spl;
};

&main_uart0 {
	//u-boot,dm-spl;
};

&main_uart0_pins_default {
	//u-boot,dm-spl;
};

&main_uart2 {
	u-boot,dm-spl;
};

&main_uart2_pins_default {
	u-boot,dm-spl;
};

&main_uart1 {
	u-boot,dm-spl;
};

&cbass_mcu {
	u-boot,dm-spl;
};

&cbass_wakeup {
	u-boot,dm-spl;
};

&mcu_pmx0 {
	u-boot,dm-spl;
};

&wkup_uart0 {
	u-boot,dm-spl;
};

&main_i2c0 {
	u-boot,dm-spl;
};

&main_i2c0_pins_default {
	u-boot,dm-spl;
};

&sdhci0 {
	u-boot,dm-spl;
};

&sdhci1 {
	u-boot,dm-spl;
};

&main_mmc1_pins_default {
	u-boot,dm-spl;
};

&usbss0 {
	u-boot,dm-spl;
};

&usb0 {
	dr_mode = "peripheral";
	/* Since role switching is not supported in U-Boot */
	/delete-property/ extcon;
	u-boot,dm-spl;
};

&usbss1 {
	u-boot,dm-spl;
};

&usb1 {
	u-boot,dm-spl;
};

&main_usb1_pins_default {
	u-boot,dm-spl;
};

&cpsw3g {
	reg = <0x0 0x8000000 0x0 0x200000>,
	      <0x0 0x43000200 0x0 0x8>;
	reg-names = "cpsw_nuss", "mac_efuse";
	/delete-property/ ranges;
	u-boot,dm-spl;

	cpsw-phy-sel@04044 {
		compatible = "ti,am64-phy-gmii-sel";
		reg = <0x0 0x00104044 0x0 0x8>;
		u-boot,dm-spl;
	};
};

&cpsw_port2 {
	status = "disabled";
};

&main_bcdma {
	u-boot,dm-spl;
};

&main_pktdma {
	u-boot,dm-spl;
};

&fss {
	u-boot,dm-spl;
};

&ospi0_pins_default {
	u-boot,dm-spl;
};

&cpsw_port1 {
	u-boot,dm-spl;
};

&main_rgmii1_pins_default {
	u-boot,dm-spl;
};

&main_mdio1_pins_default {
	u-boot,dm-spl;
};

&cpsw3g_phy0 {
	u-boot,dm-spl;
};

&dmsc {
	u-boot,dm-spl;
	k3_sysreset: sysreset-controller {
		compatible = "ti,sci-sysreset";
		u-boot,dm-spl;
	};
};

Fullscreen k3-am625-r5-sk.txt Download

// SPDX-License-Identifier: GPL-2.0
/*
 * AM625 SK dts file for R5 SPL
 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "k3-am625-sk.dts"
#include "k3-am62x-sk-ddr4-1600MTs.dtsi"
#include "k3-am62-ddr.dtsi"

#include "k3-am625-sk-u-boot.dtsi"
#include "k3-am62x-r5-sk-common.dtsi"

Fullscreen 8055.k3-am62x-sk-common-u-boot.txt Download

// SPDX-License-Identifier: GPL-2.0
/*
 * Common AM62x SK dts file for SPLs
 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/ {
	chosen {
		stdout-path = "serial4:115200n8";
		tick-timer = &timer1;
	};

	aliases {
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
	};

	memory@80000000 {
		u-boot,dm-spl;
	};
};

&cbass_main{
	u-boot,dm-spl;

	timer1: timer@2400000 {
		compatible = "ti,omap5430-timer";
		reg = <0x00 0x2400000 0x00 0x80>;
		ti,timer-alwon;
		clock-frequency = <25000000>;
		u-boot,dm-spl;
	};
};

&dmss {
	u-boot,dm-spl;
};

&secure_proxy_main {
	u-boot,dm-spl;
};

&dmsc {
	u-boot,dm-spl;
};

&k3_pds {
	u-boot,dm-spl;
};

&k3_clks {
	u-boot,dm-spl;
};

&k3_reset {
	u-boot,dm-spl;
};

&wkup_conf {
	u-boot,dm-spl;
};

&chipid {
	u-boot,dm-spl;
};

&main_pmx0 {
	u-boot,dm-spl;
};

&main_uart0 {
	//u-boot,dm-spl;
};

&main_uart0_pins_default {
	//u-boot,dm-spl;
};

&main_uart2 {
	u-boot,dm-spl;
};

&main_uart2_pins_default {
	u-boot,dm-spl;
};

&main_uart1 {
	u-boot,dm-spl;
};

&cbass_mcu {
	u-boot,dm-spl;
};

&cbass_wakeup {
	u-boot,dm-spl;
};

&mcu_pmx0 {
	u-boot,dm-spl;
};

&wkup_uart0 {
	u-boot,dm-spl;
};

&main_i2c0 {
	u-boot,dm-spl;
};

&main_i2c0_pins_default {
	u-boot,dm-spl;
};

&sdhci0 {
	u-boot,dm-spl;
};

&sdhci1 {
	u-boot,dm-spl;
};

&main_mmc1_pins_default {
	u-boot,dm-spl;
};

&usbss0 {
	u-boot,dm-spl;
};

&usb0 {
	dr_mode = "peripheral";
	/* Since role switching is not supported in U-Boot */
	/delete-property/ extcon;
	u-boot,dm-spl;
};

&usbss1 {
	u-boot,dm-spl;
};

&usb1 {
	u-boot,dm-spl;
};

&main_usb1_pins_default {
	u-boot,dm-spl;
};

&cpsw3g {
	reg = <0x0 0x8000000 0x0 0x200000>,
	      <0x0 0x43000200 0x0 0x8>;
	reg-names = "cpsw_nuss", "mac_efuse";
	/delete-property/ ranges;
	u-boot,dm-spl;

	cpsw-phy-sel@04044 {
		compatible = "ti,am64-phy-gmii-sel";
		reg = <0x0 0x00104044 0x0 0x8>;
		u-boot,dm-spl;
	};
};

&cpsw_port2 {
	status = "disabled";
};

&main_bcdma {
	u-boot,dm-spl;
};

&main_pktdma {
	u-boot,dm-spl;
};

&fss {
	u-boot,dm-spl;
};

&ospi0_pins_default {
	u-boot,dm-spl;
};

&cpsw_port1 {
	u-boot,dm-spl;
};

&main_rgmii1_pins_default {
	u-boot,dm-spl;
};

&main_mdio1_pins_default {
	u-boot,dm-spl;
};

&cpsw3g_phy0 {
	u-boot,dm-spl;
};

&dmsc {
	u-boot,dm-spl;
	k3_sysreset: sysreset-controller {
		compatible = "ti,sci-sysreset";
		u-boot,dm-spl;
	};
};

0 Bin Liu over 1 year ago in reply to sivakumar parames

TI__Guru**** 172861 points

Hi Siva,

Other than these 3 attached device tree files (the 4th one is duplicate), do you have any other change in the u-boot device tree?

0 Bin Liu over 1 year ago in reply to Bin Liu

TI__Guru**** 172861 points

Bin Liu said:
Please attach the file <SDK>/board-support/u-boot_build/r5/arch/arm/dts/k3-am625-r5-sk.dtb for me to review.

I need to see your k3-am625-r5-sk.dtb file, not dts source code.

0 sivakumar parames over 1 year ago in reply to Bin Liu

Prodigy 185 points

HI Bin, I followed the exact procedure given in
e2e.ti.com/.../4916153

0 sivakumar parames over 1 year ago in reply to Bin Liu

Prodigy 185 points

Hi Bin,

Unfortunately I couldnt upload as file. I attached in drive and link below.

https://drive.google.com/file/d/1wCNfT8_pUi8niQa2rNPCIEiodQ6p7Hfd/view?usp=drive_link

thanks,

siva.

0 Bin Liu over 1 year ago in reply to sivakumar parames

TI__Guru**** 172861 points

Hi Siva,

I am unable to access the link through firewall. What was the error you got when upload as file? Can you please zip the dtb file then upload it?

0 sivakumar parames over 1 year ago in reply to Bin Liu

Prodigy 185 points

Here you go..

drive.google.com/.../view

0 Bin Liu over 1 year ago in reply to sivakumar parames

TI__Guru**** 172861 points

Hi Siva,

I am unable to access Google drive due to company firewall. I was asking if you could zip the file and upload it on this e2e thread.

0 sivakumar parames over 1 year ago in reply to Bin Liu

Prodigy 185 points

Hi Bin, Sorry for the confusion. i thought you needed zip file in google drive. Pls find the attached file.

k3-am625-r5-sk.zip

0 Bin Liu over 1 year ago in reply to sivakumar parames

TI__Guru**** 172861 points

Hi Siva,

Thanks for uploading the file.

sivakumar parames said:
k3_ddrss memorycontroller@f300000: clk get failed-2

I will talk to our DDR expert to understand what could cause the DDR clock init to be failed, and get back to you.

0 sivakumar parames over 1 year ago in reply to Bin Liu

Prodigy 185 points

Hi Bin,

I would be glad to hear any update on this.

thanks,

siva.

0 Bin Liu over 1 year ago in reply to sivakumar parames

TI__Guru**** 172861 points

Hi Siva,

Please apply the following u-boot patch and attach the u-boot console log. This should print some debug messages about the failure.

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 11c982ca9287..e45655137439 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -5,7 +5,7 @@
  * Copyright (c) 2016, NVIDIA CORPORATION.
  * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
  */
-
+#define DEBUG
 #include <common.h>
 #include <clk.h>
 #include <clk-uclass.h>

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AM625: console output UART0 to UART2