• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 283 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM6442: DDR4 CLK Setting

Kanae
Guru 10095 points
Part Number: AM6442

Hi Support Team,

In case of using DDR4-1600MT, the clock from PLL12 is 800MHz.
Am I correct in understanding that the clock is 800MHz in this configuration?
I have checked as follows, but just to be sure, please let me know if you have any concerns.

Best Regards,
Kanae

  • 0
    TI__Guru* 86870 points

    Kanae, no, PLL12 HSDIV0 should be 400MHz.  This will yield a memory clock of 800MHz, and data rate of 1600MHz.  There is a separate PLL in the DDR subsystem which produces the 2x and 4x clock frequencies that are required for the DDR controller and PHY to operate.

    Regards,

    James

  • 0 in reply to JJD
    Guru 10095 points

    Hi James,

    Thank you for your reply.
    Could you please let me confirm a few more things?

    1. PLL12 HSDIV0 is a fixed value of 400MHz?

    2. Is my understanding correct that the PLL12 HSDIV0 doubles 400MHz with the DDR subsystem PLL
    　to generate 800HMz?

      James said:
     There is a separate PLL in the DDR subsystem which produces the 2x and 4x clock frequencies
     that are required for the DDR controller and PHY to operate.

      Could you please clarify the documentation that describes which registers are used to make this setting?

    Best Regards,
    Kanae

  • +1 in reply to Kanae
    TI__Guru* 86870 points

    1. Yes, it will be a fixed value if you choose 800MHz memory clock operating frequency in the DDR register configuration tool.  Other frequencies will have a different PLL configuration, but the PLL will always be half of the memory clock frequency

    2. Yes

    There is nothing that configures the DDR PHY PLL.  This is inherent in the design.

    Regards,

    James

  • 0 in reply to JJD
    Guru 10095 points

    　Hi James,

    Thank you for your reply.

    I could understand that there is a separate PLL in the DDR subsystem
    which produces the 2x and 4x clock frequencies as it  is inherent in the design.
    Could you please provide a document that states this information,
    I have checked the TRM but cannot find it.

    Best Regards,
    Kanae

  • +1 in reply to Kanae
    TI__Guru* 86870 points

    Kanae, this would be in a internal design doc which i cannot share.  However, the PLLs are shown in the block diagram in the TRM.

    Regards,

    James

  • 0 in reply to JJD
    Guru 10095 points

    Hi James,

    Thank you for your support!
    I will share it with my customer.

    Best Regards,
    Kanae