DDR pll clock 2 can't pass to SYSCLK10.

Hi Kenji Sasaki,

How are you conforming taht the DDR frequency is 800MHz?

Could you please get these register details DDRPLL_CTRL, DDRPLL_PWD, DDRPLL_FREQ2, DDRPLL_DIV2. So that we can analize more on this.

Thanks & Best Regards

Anilkumar

Dear Anilkumar

To check DDR3 frequency, I used Oscilloscope. (DDR0_CK0/CK0N)

However, my oscilloscope can sample up to 5G so it might be wrong .

DDRPLL_CTRL = 0x003B0188

DDRPLL_PWD = 0x00000000

DDRPLL_FREQ2 = 0x98D99999

DDEPLL_DIV2 = 0x0000011E

By the way, I also check freqeuncy CLKOUT line.

CM_CLKOUT_CTRL was set 0x81.

At this time, CLKOUT was outputting the frequency which is 27 MHz. 

Up to reference.

Best Regards

Kenji

Hi Kenji,

I have a quick question,

NOR boot mode is already supported then why are you doing once again?

Refer http://software-dl.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/DM816x_04_00/04_00_00_12/index_FDS.html

From the status of CM_CLKOUT_CTRL register I can say that DDR frequency is 27MHz

I missed out one register in my earlier post, whcih is need for knowling the frequency of DDR from DDRPLL_* registers. That is "DDRPLL_DIV1"

Regards

Anilkumar

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Hi Kenji,

I have a quick question,

NOR boot mode is already supported then why are you doing once again?

Refer http://software-dl.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/DM816x_04_00/04_00_00_12/index_FDS.html

From the status of CM_CLKOUT_CTRL register I can say that DDR frequency is 27MHz

I missed out one register in my earlier post, whcih is need for knowling the frequency of DDR from DDRPLL_* registers. That is "DDRPLL_DIV1"

Regards

Anilkumar