Part Number: AM6442
Per the AM6442 TRM (SPRUIM2H) Figure 12-344 (on page 6935) the CPPI_ICLK for the CPSW0 block is derived from PLLCTRL0 via MAIN_SYSCLK0_RSTISO/2.
Per SPRUIM2H Table 4-35 the boot ROM configures MAIN_SYSCLK0 for 500MHz by default. Which would make the CPPI_ICLK to be 500MHz / 2 = 250MHz.
SPRUIM2H Table 12-641 says CPPI_ICLK is the "CPPI packet streaming interface clock (333MHz)".
So is it possible to run CPPI_ICLK at 250MHz (boot loader default), or must it changed to be 333MHz (like in table 12-641)?
It doesn't seem like an ICLK is in the same category as something like the GMII_RFT_CLK that must run at a specific frequency (250MHz) to support an external interface standard (RGMII). Is there some special reason why CPPI_ICLK needs to be 333MHz? Or is that table comment just left over from copy/pasting the manual section from somewhere else?
I understand that lowering it too much could result in reduced performance, but will it still work (just slower)? Mainly I want to avoid changing MAIN_SYSCLK0 to 666MHz because it then affects clocks to many other peripherals throughout the system and then all that code needs to change.
