DRA829J-Q1: ADC input current limitation

Peter Fritzenschaft

Part Number: DRA829J-Q1
Other Parts Discussed in Thread: DRA829J

Hello,

we want to use the DRA829J ADC for monitoring of supply voltages, which can be present even when the DRA829J is not supplied.

The DRA829J data sheet SPRSP35J maximum ratings give a steady state max. voltage at "all other IO pins" of IO supply voltage +0.3V.

Is it allowed to exceed this value when the current to the pin (especially ADC inputs) is limited to e.g. 5mA?

Regards, Peter

0 Kevin Lavery 8 months ago

Peter,

When current is injected into the ADC, it tends to flow through VDDA_ADC. In your system, will VDDA_ADC sink that current in the power OFF case?

Kevin

0 Peter Fritzenschaft 8 months ago

Kevin,

VDDA_ADC will sink that current in the power OFF case, but this current could lift up VDDA_ADC before it is powered by the PMIC Circuit (PDN-0C).

Could you give a limit for VDDA_ADC in this case so we could reduce the current flowing into the ADC pins to an acceptable value.

Peter

+1 Kevin Lavery 8 months ago in reply to Peter Fritzenschaft

If VDDA_ADC will sink current, then it is safe to limit the current to 4mA or less.

Kevin

0 Peter Fritzenschaft 8 months ago in reply to Kevin Lavery

Hello Kevin,

is this limit of 4mA applicable per ADC input pin, or is it the max. limit for the sum of all 16 ADC input pins together?

Regards, Peter

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