SK-AM68: IBIS Model

My customer is looking for the IBIS model for the specific DRAM. Do we support that DRAM and do we have an IBIS model for it? 

Hello Matthew,

Ok, I will redirect & request our hardware apps team to comment on your query.

Thanks.

Hi Kyle, 

The customer has been reaching out to Micron for the model and they have not responded. Do we have a copy of the IBIS model that we can share for the MT53E2G32D4DE-046 AUT:C ? if not the project will not go to production and we will not realize revenue. 

Matthew,

We can reach out to the memory vendor (as a second requestor) to ask if they can provide the corresponding model to the mutual customer, but ultimately the customer will need to get the model from the memory vendor and not TI.

Regards,
Kevin

Please reach out on behalf of Fractal Audio and ask them for the model. My customer has reached out multiple times and has not be answered. 

Matthew Baker said:

Please reach out on behalf of Fractal Audio and ask them for the model.

Doing so now.

Updating E2E ticket with latest information:

- Customer currently has access to the LPDDR4 IBIS model.
- Customer looking for AM68 package skew spreadsheet.

Regards,
Kevin

We’ve completed our SI/PI analysis.  The only issue we’ve encountered is the skew of the CSN signals.  Since there is only a single load on these signals vs. a double-load on the address lines CSN is arriving 50ps earlier.

Can you run this by engineering to make sure this is acceptable.  Note that we copied the DDR layout exactly from the Starter Kit.

XM-1 DSP Board SIPI Simulation Results Document Rev 0.1.doc

I don't see any issue with the provided data.  The simulations look very clean, thus I'm guessing a 2D or 2.5D simulation tool is used.  These tools don't accurately model vias - thus recommend a true 3D tool for more accurate representation of the eye.  You mentioned following an existing TI layout, which is strongly recommended.

Is the 50ps skew of CSN something we should correct?  We can make the CSN net longer to compensate.  We are concerned that the hold time could be violated.

Matthew,

Chip select signals can be individually delayed by the controller / PHY, so some skew difference can be tolerated. My understanding is that a difference of 50 ps of skew between CS signals compared to CA signals  should be comparable to the AM68 EVM/SK board designs. 

Regards,
Kevin