PROCESSOR-SDK-J784S4: MAIN UART receiving(RX) not working.

Hi Prasad,

Do you have the same issue when using MCU_UART?

Thanks,

Neehar

Hello Neehar,

There is no issue with MCU_UART and MAIN_UART8, both RX and TX working fine.

there is an issue with WAKUP_UART0 and MAIN_UARTS, only TX is working. and RX is not working.

Regards,

Prasad.

Hi Prasad,

The pinmux in your device tree looks correct and matches sysconfig.

Let me look into this and get back to you.
Thanks,

Neehar

Hello Neehar,

any update on this issue?

Regards,

Prasad.

Hi Prasad,

I have reassigned this thread to another expert who will be able to help. Thank you for your patience.
Thanks,
Neehar

Hello Prasad,

Are you using TI EVM or a custom board? Assuming TI EVM:

&wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};

Can you make it

&wkup_uart0 {
status = "Okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};

For other UARTs:

https://dev.ti.com/sysconfig/#/config/?args=--device%20J784S4_TDA4AP_TDA4VP_TDA4AH_TDA4VH_AM69x%20--part%20Default%20--package%20ALY

&main_pmx0 {
    myuart1_pins_default: myuart1-default-pins {
        pinctrl-single,pins = <
            J784S4_IOPAD(0x0c4, PIN_INPUT, 11) /* (AD36) ECAP0_IN_APWM_OUT.UART2_CTSn */
            J784S4_IOPAD(0x0c8, PIN_INPUT, 11) /* (AJ32) EXT_REFCLK1.UART2_RTSn */
            J784S4_IOPAD(0x064, PIN_INPUT, 11) /* (AF38) MCAN0_TX.UART2_RXD */
            J784S4_IOPAD(0x068, PIN_INPUT, 11) /* (AE38) MCAN0_RX.UART2_TXD */
        >;
    };

};

You will need to add similar pinmux nodes & hook them like how it is done for WKUP_UART0, MAIN)UART8.

- Keerthy

Hello Keerthy,

Thanks for the info.

yes I am working on TI EVM J784s4.

I will check your suggestions and come back.

I have following query regarding UART.

I would like to change the alias name for UART8 from Serial2 to some other name EX: Serial8, can you please help  for the same?

what are the files i have to modify in u-boot, kernel, spl?

k3-j784s4-evm.dts:

default name:

aliases {
serial0 = &wkup_uart0;
serial1 = &main_uart5;
serial2 = &main_uart8;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
i2c0 = &main_i2c0;
};

new name:

aliases {
serial0 = &wkup_uart0;
serial1 = &main_uart5;
serial8 = &main_uart8;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
i2c0 = &main_i2c0;
};

Regards,

Prasad

Hi Prasad,

By default serial2 is used in the SDK for console. So we use that. I believe you will have to change the ttyS2 to ttyS8 in the bootargs.
More changes might be needed at the file system level. I am not sure on that.
That is the change I believe is needed. I recommend to keep it serial serial2.

- Keerthy

Hello Keerthy,

We have a requirement to use wkup_uart0 as a debug console on the J784s4-EVM board.

I would like to configure wkup_uart0 as a debug console for all the components like tiboot3.bin, tispl.bin and ATF and u-boot and kernel.

i followed your below forum, but i didn't succeeded. i am able to configure wkup_uart0 for u-boot and kernel and could see the prints on the wkup_uart0 but terminal is not receiving any inputs.

also modified ATF source  and copied bl31 to prebuilt directory and rebuilt the u-boot. 

but booting is stuck before ATF. could you please list what are the files i have to modify from system level to use wkup_uart0 as a debug console?

e2e.ti.com/.../3718577

regards,

Prasad.

Prasad,

We have reserved the wkup_uart for tifs prints. So the M3 also adds prints on the console. It's better to use the MCU-uart.

Best Regards,

Keerthy 

Hello Keerthy,

Thanks for the quick response !!!.

But we have a requirement to use wkup_uart0 for debug console, I believe we can still use wkup_uart0 for debug and MCU-uart for tifs.

can you please help, how to configure wkup_uart0 for debug console and MCU-uart for tifs prints?

can you please provide some steps ?

Regards,

Prasad.

Hello Keerthy,

I configured main_uart5 as debug console in  linux device-tree k3-j784s4-evm.dts file and i could see the kernel logs on the main_uart5.

as you can see the prints switched from UART8 to UART5 console, but UART5 console is responding for my inputs.

UART RX is not working ? or do we need to make any other changes apart from device tree?

Can you please provide some inputs here?

This issue i have seen even with WKUP_UART0 as well. console is not responding for any inputs.

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
 *
 * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458
 */

/dts-v1/;

#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/gpio/gpio.h>
#include "k3-j784s4.dtsi"

/ {
	compatible = "ti,j784s4-evm", "ti,j784s4";
	model = "Texas Instruments J784S4 EVM";

	chosen {
		stdout-path = "serial2:115200n8";
	};

	aliases {
		serial0 = &wkup_uart0;
		serial1 = &mcu_uart0;
		serial2 = &main_uart5;
		mmc0 = &main_sdhci0;
		mmc1 = &main_sdhci1;
		i2c0 = &main_i2c0;
	};

	memory@80000000 {
		device_type = "memory";
		/* 32G RAM */
		reg = <0x00 0x80000000 0x00 0x80000000>,
		      <0x08 0x80000000 0x07 0x80000000>;
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		 /* global cma region */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x00 0x70000000>;
			linux,cma-default;
		};

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>;
			no-map;
		};

		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0000000 0x00 0x100000>;
			no-map;
		};

		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			no-map;
		};

		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1000000 0x00 0x100000>;
			no-map;
		};

		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa5000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa5100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa6000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa6100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa7000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa7100000 0x00 0xf00000>;
			no-map;
		};

		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa8000000 0x00 0x100000>;
			no-map;
		};

		c71_0_memory_region: c71-memory@a8100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa8100000 0x00 0xf00000>;
			no-map;
		};

		c71_1_dma_memory_region: c71-dma-memory@a9000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa9000000 0x00 0x100000>;
			no-map;
		};

		c71_1_memory_region: c71-memory@a9100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa9100000 0x00 0xf00000>;
			no-map;
		};

		c71_2_dma_memory_region: c71-dma-memory@aa000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xaa000000 0x00 0x100000>;
			no-map;
		};

		c71_2_memory_region: c71-memory@aa100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xaa100000 0x00 0xf00000>;
			no-map;
		};

		c71_3_dma_memory_region: c71-dma-memory@ab000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xab000000 0x00 0x100000>;
			no-map;
		};

		c71_3_memory_region: c71-memory@ab100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xab100000 0x00 0xf00000>;
			no-map;
		};
	};

	evm_12v0: regulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: regulator-vsys3v3 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: regulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: regulator-sd {
		/* Output of TPS22918 */
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
	};

	vdd_sd_dv: regulator-TLV71033 {
		/* Output of TLV71033 */
		compatible = "regulator-gpio";
		regulator-name = "tlv71033";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_5v0>;
		gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};

	dp0_pwr_3v3: regulator-dp0-prw {
		compatible = "regulator-fixed";
		regulator-name = "dp0-pwr";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&exp4 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	dp0: dp0-connector {
		compatible = "dp-connector";
		label = "DP0";
		type = "full-size";
		dp-pwr-supply = <&dp0_pwr_3v3>;

		port {
			dp0_connector_in: endpoint {
				remote-endpoint = <&dp0_out>;
			};
		};
	};

	vsys_io_1v8: regulator-vsys-io-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_io_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_io_1v2: regulator-vsys-io-1v2 {
		compatible = "regulator-fixed";
		regulator-name = "vsys_io_1v2";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		regulator-always-on;
		regulator-boot-on;
	};

	edp1_refclk: clock-edp1-refclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <19200000>;
	};

	dp1_pwr_3v3: regulator-dp1-prw {
		compatible = "regulator-fixed";
		regulator-name = "dp1-pwr";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */
		enable-active-high;
		regulator-always-on;
	};

	transceiver1: can-phy0 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>;
	};

	transceiver2: can-phy1 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
	};

	transceiver3: can-phy2 {
		/* standby pin has been grounded by default */
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
	};
};

&wkup_pmx1 {
	pmic_irq_pins_default: pmic-irq-pins-default {
		pinctrl-single,pins = <
			/* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */
			J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7)
		>;
	};

	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */
			J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */
			J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */
			J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */
			J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */
			J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */
			J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */
			J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */
		>;
	};

	mcu_fss0_ospi0_pins1_default: mcu-fss0-ospi0-pins1-default {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */
			J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */
		>;
	};
};

&wkup_pmx2 {
	status = "okay";
	wkup_i2c0_pins_default: wkup_i2c0_pins_default {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
			J784S4_WKUP_IOPAD(0x09C, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
		>;
	};

	mcu_uart0_pins_default: mcu-uart0-pins-default {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) MCU_UART0_CTSn */
			J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) MCU_UART0_RTSn */
			J784S4_WKUP_IOPAD(0x08C, PIN_INPUT, 0) /* (K38) MCU_UART0_RXD */
			J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) MCU_UART0_TXD */
		>;
	};

	wkup_uart0_pins_default: wkup-uart0-pins-default {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
			J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */
		>;
	};
	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
			J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
			J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
			J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
			J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
			J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
			J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
			J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
			J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
			J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
			J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
			J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
		>;
	};

	mcu_mdio_pins_default: mcu-mdio-pins-default {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
			J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
		>;
	};

	mcu_adc0_pins_default: mcu-adc0-pins-default {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */
			J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */
			J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */
			J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */
			J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */
			J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */
			J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */
			J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */
		>;
	};

	mcu_adc1_pins_default: mcu-adc1-pins-default {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */
			J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */
			J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */
			J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */
			J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */
			J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */
			J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */
			J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */
		>;
	};

};

&wkup_gpio0 {
	status = "okay";
};

&wkup_gpio_intr {
	status = "okay";
};

&wkup_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_i2c0_pins_default>;
	clock-frequency = <400000>;
	tps659413: pmic@48 {
		compatible = "ti,tps6594-q1";
		reg = <0x48>;
		system-power-controller;
		pinctrl-names = "default";
		pinctrl-0 = <&pmic_irq_pins_default>;
		interrupt-parent = <&wkup_gpio0>;
		interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
		ti,primary-pmic;

		gpio-controller;
		#gpio-cells = <2>;

		buck12-supply = <&vsys_3v3>;
		buck3-supply = <&vsys_3v3>;
		buck4-supply = <&vsys_3v3>;
		buck5-supply = <&vsys_3v3>;
		ldo1-supply = <&vsys_3v3>;
		ldo2-supply = <&vsys_3v3>;
		ldo3-supply = <&vsys_3v3>;
		ldo4-supply = <&vsys_3v3>;

		regulators {
			bucka12: buck12 {
				regulator-name = "vdd_ddr_1v1";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-boot-on;
				regulator-always-on;
			};

			bucka3: buck3 {
				regulator-name = "vdd_ram_0v85";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			bucka4: buck4 {
				regulator-name = "vdd_io_1v8";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			bucka5: buck5 {
				regulator-name = "vdd_mcu_0v85";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldoa1: ldo1 {
				regulator-name = "vdd_mcuio_1v8";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldoa2: ldo2 {
				regulator-name = "vdd_mcuio_3v3";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldoa3: ldo3 {
				regulator-name = "vds_dll_0v8";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldoa4: ldo4 {
				regulator-name = "vda_mcu_1v8";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&main_pmx0 {
	main_cpsw2g_pins_default: main-cpsw2g-pins-default {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */
			J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */
			J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */
			J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */
			J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */
			J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */
			J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */
			J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */
			J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */
			J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */
			J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */
			J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */
		>;
	};

	main_cpsw2g_mdio_pins_default: main-cpsw2g-mdio-pins-default {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */
			J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */
		>;
	};

    	main_uart3_pins_default: main_uart3-default-pins {
        	pinctrl-single,pins = <
            		J784S4_IOPAD(0x074, PIN_INPUT, 11) /* (AC33) MCAN2_TX.UART3_RXD */
            		J784S4_IOPAD(0x078, PIN_INPUT, 11) /* (AH37) MCAN2_RX.UART3_TXD */
        	>;
    	};
    	
    	    main_uart5_pins_default: main_uart5-default-pins {
        pinctrl-single,pins = <
            J784S4_IOPAD(0x008, PIN_INPUT, 11) /* (AJ33) MCAN12_RX.UART5_RXD */
            J784S4_IOPAD(0x004, PIN_INPUT, 11) /* (AG36) MCAN12_TX.UART5_TXD */
        >;
    };
    
	main_uart8_pins_default: main-uart8-pins-default {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
			J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */
			J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
			J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
		>;
	};

	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
			J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
		>;
	};

	main_i2c5_pins_default: main-i2c5-pins-default {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */
			J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */
		>;
	};

	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
			J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
			J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
			J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
			J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
			J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
			J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
			J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
		>;
	};

	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
		>;
	};

	dp0_pins_default: dp0-pins-default {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
		>;
	};

	main_i2c4_pins_default: main-i2c4-pins-default {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
			J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
		>;
	};

	main_usbss0_pins_default: main-usbss0-pins-default {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
		>;
	};

	main_mcan16_pins_default: main-mcan16-default-pins {
		pinctrl-single,pins = <
			J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */
			J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */
		>;
	};
};

&wkup_pmx0 {
	typec_dir_gpio_pins_default: typec-dir-gpio-pins-default {
		pinctrl-single,pins = <
			/* (A33) MCU_OSPI0_CSn1.WKUP_GPIO0_28 */
			J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 7)
		>;
	};
	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */
			J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */
			J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */
			J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */
			J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */
			J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */
			J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */
			J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */
			J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */
			J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */
			J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
		>;
	};
};

&wkup_pmx2{
	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */
			J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */
		>;
	};

	mcu_mcan1_pins_default: mcu-mcan1-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */
			J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */
		>;
	};

	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */
		>;
	};

	mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
		pinctrl-single,pins = <
			J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */
		>;
	};
};

&main_uart3 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart3_pins_default>;
};

&main_uart5 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart5_pins_default>;
};

&main_uart8 {
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart8_pins_default>;
};

&ufs_wrapper {
	status = "okay";
};

&fss {
	status = "okay";
};

&ospi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;

	ospi0_nor: flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "ospi.tiboot3";
				reg = <0x0 0x100000>;
			};

			partition@100000 {
				label = "ospi.tispl";
				reg = <0x100000 0x200000>;
			};

			partition@300000 {
				label = "ospi.u-boot";
				reg = <0x300000 0x400000>;
			};

			partition@700000 {
				label = "ospi.env";
				reg = <0x700000 0x40000>;
			};

			partition@740000 {
				label = "ospi.env.backup";
				reg = <0x740000 0x40000>;
			};

			partition@800000 {
				label = "ospi.rootfs";
				reg = <0x800000 0x37c0000>;
			};

			partition@3fc0000 {
				label = "ospi.phypattern";
				reg = <0x3fc0000 0x40000>;
			};
		};
	};

	ospi0_nand: nand@0 {
		compatible = "spi-nand";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
		status = "disabled";

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "ospi_nand.tiboot3";
				reg = <0x0 0x100000>;
			};

			partition@100000 {
				label = "ospi_nand.tispl";
				reg = <0x100000 0x200000>;
			};

			partition@300000 {
				label = "ospi_nand.u-boot";
				reg = <0x300000 0x400000>;
			};

			partition@700000 {
				label = "ospi_nand.env";
				reg = <0x700000 0x40000>;
			};

			partition@740000 {
				label = "ospi_nand.env.backup";
				reg = <0x740000 0x40000>;
			};

			partition@2000000 {
				label = "ospi_nand.rootfs";
				reg = <0x2000000 0x5fc0000>;
			};

			partition@7fc0000 {
				label = "ospi_nand.phypattern";
				reg = <0x7fc0000 0x40000>;
			};
		};
	};
};

&ospi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;

	flash@0{
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <40000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <2>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "qspi.tiboot3";
				reg = <0x0 0x100000>;
			};

			partition@100000 {
				label = "qspi.tispl";
				reg = <0x100000 0x200000>;
			};

			partition@300000 {
				label = "qspi.u-boot";
				reg = <0x300000 0x400000>;
			};

			partition@700000 {
				label = "qspi.env";
				reg = <0x700000 0x40000>;
			};

			partition@740000 {
				label = "qspi.env.backup";
				reg = <0x740000 0x40000>;
			};

			partition@800000 {
				label = "qspi.rootfs";
				reg = <0x800000 0x37c0000>;
			};

			partition@3fc0000 {
				label = "qspi.phypattern";
				reg = <0x3fc0000 0x40000>;
			};
		};

	};
};

&main_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;

	clock-frequency = <400000>;

	exp1: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ",
				  "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ",
				  "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#",
				  "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3",
				  "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ";
	};

	exp2: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN",
				  "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0",
				  "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#",
				  "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ",
				  "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1",
				  "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ",
				  "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ",
				  "USER_INPUT1", "USER_LED1", "USER_LED2";
	};
};

&main_sdhci0 {
	/* eMMC */
	status = "okay";
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	no-mmc-hs400;
};

&main_sdhci1 {
	/* SD card */
	status = "okay";
	pinctrl-0 = <&main_mmc1_pins_default>;
	pinctrl-names = "default";
	disable-wp;
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vdd_sd_dv>;
};

&serdes0 {
	status = "okay";
	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
	};

	serdes0_usb_link: phy@3 {
		reg = <3>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz0 4>;
	};
};

&serdes_wiz0 {
	status = "okay";
};

&usb_serdes_mux {
	idle-states = <0>; /* USB0 to SERDES lane 3 */
};

&usbss0 {
	status = "okay";
	pinctrl-0 = <&main_usbss0_pins_default>;
	pinctrl-names = "default";
	ti,vbus-divider;
};

&usb0 {
	dr_mode = "otg";
	maximum-speed = "super-speed";
	phys = <&serdes0_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

&serdes1 {
	status = "okay";
	serdes1_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
	};
};

&serdes_wiz1 {
	status = "okay";
};

&pcie0_rc {
	status = "okay";
	reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
	phys = <&serdes1_pcie_link>;
	phy-names = "pcie-phy";
};

&pcie0_ep {
	phys = <&serdes1_pcie_link>;
	phy-names = "pcie-phy";
};

&pcie1_rc {
	status = "okay";
	num-lanes = <2>;
	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie-phy";
};

&pcie1_ep {
	num-lanes = <2>;
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie-phy";
};

&serdes_ln_ctrl {
	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
		<J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
		<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
		<J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
		<J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
};

&main_gpio0 {
	status = "okay";
};

&mcu_cpsw {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_pins_default>;

	cpts@3d000 {
		/* Map HW4_TS_PUSH to GENF1 */
		ti,pps = <3 1>;
	};
};

&davinci_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_mdio_pins_default>;

	mcu_phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&mcu_cpsw_port1 {
	status = "okay";
	phy-mode = "rgmii-rxid";
	phy-handle = <&mcu_phy0>;
};

&main_cpsw1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_cpsw2g_pins_default>;
};

&main_cpsw1_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&main_cpsw2g_mdio_pins_default>;

	main_phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&main_cpsw1_port1 {
	status = "okay";
	phy-mode = "rgmii-rxid";
	phy-handle = <&main_phy0>;
};

&serdes_refclk {
	clock-frequency = <100000000>;
};

&dss {
	status = "okay";
	assigned-clocks = <&k3_clks 218 2>,
			  <&k3_clks 218 5>,
			  <&k3_clks 218 14>,
			  <&k3_clks 218 18>;
	assigned-clock-parents = <&k3_clks 218 3>,
				 <&k3_clks 218 7>,
				 <&k3_clks 218 16>,
				 <&k3_clks 218 22>;
};

&serdes_wiz4 {
	status = "okay";
};

&serdes4 {
	status = "okay";
	serdes4_dp_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <4>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_DP>;
		cdns,max-bit-rate = <2700>;
		resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
			 <&serdes_wiz4 3>, <&serdes_wiz4 4>;
	};
};

&mhdp {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&dp0_pins_default>;
	phys = <&serdes4_dp_link>;
	phy-names = "dpphy";
};

&dss_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		dpi0_out: endpoint {
			remote-endpoint = <&dp0_in>;
		};
	};

	port@2 {
		reg = <2>;
		dpi2_out: endpoint {
			remote-endpoint = <&dsi0_in>;
		};
	};
};

&main_i2c4 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c4_pins_default>;
	clock-frequency = <400000>;

	exp4: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	dsi_edp_bridge: dsi-edp-bridge@2c {
		compatible = "ti,sn65dsi86";
		reg = <0x2c>;

		clock-names = "refclk";
		clocks = <&edp1_refclk>;

		enable-gpios = <&exp4 2 GPIO_ACTIVE_HIGH>;

		vpll-supply = <&vsys_io_1v8>;
		vccio-supply = <&vsys_io_1v8>;
		vcca-supply = <&vsys_io_1v2>;
		vcc-supply = <&vsys_io_1v2>;

		dsi_edp_bridge_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				dp1_in: endpoint {
					remote-endpoint = <&dsi0_out>;
				};
			};

			port@1 {
				reg = <1>;
				dp1_out: endpoint {
					remote-endpoint = <&dp1_panel_in>;
				};
			};
		};

		aux-bus {
			panel {
				compatible = "ti,panel-edp";
				power-supply = <&dp1_pwr_3v3>;

				port {
					dp1_panel_in: endpoint {
						remote-endpoint = <&dp1_out>;
					};
				};
			};
		};
	};
};

&dsi0_ports {
	port@0 {
		reg = <0>;
		dsi0_out: endpoint {
			remote-endpoint = <&dp1_in>;
		};
	};

	port@1 {
		reg = <1>;
		dsi0_in: endpoint {
			remote-endpoint = <&dpi2_out>;
		};
	};
};

&main_i2c5 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c5_pins_default>;
	clock-frequency = <400000>;

	exp5: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&mailbox0_cluster0 {
	status = "okay";
	interrupts = <436>;

	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster1 {
	status = "okay";
	interrupts = <432>;

	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster2 {
	status = "okay";
	interrupts = <428>;

	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster3 {
	status = "okay";
	interrupts = <424>;

	mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster4 {
	status = "okay";
	interrupts = <420>;

	mbox_c71_0: mbox-c71-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_c71_1: mbox-c71-1 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mailbox0_cluster5 {
	status = "okay";
	interrupts = <416>;

	mbox_c71_2: mbox-c71-2 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};

	mbox_c71_3: mbox-c71-3 {
		ti,mbox-rx = <2 0 0>;
		ti,mbox-tx = <3 0 0>;
	};
};

&mcu_r5fss0_core0 {
	status = "okay";
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
			<&mcu_r5fss0_core0_memory_region>;
};

&mcu_r5fss0_core1 {
	status = "okay";
	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
			<&mcu_r5fss0_core1_memory_region>;
};

&main_r5fss0_core0 {
	status = "okay";
	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
	memory-region = <&main_r5fss0_core0_dma_memory_region>,
			<&main_r5fss0_core0_memory_region>;
};

&main_r5fss0_core1 {
	status = "okay";
	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
	memory-region = <&main_r5fss0_core1_dma_memory_region>,
			<&main_r5fss0_core1_memory_region>;
};

&main_r5fss1_core0 {
	status = "okay";
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
	memory-region = <&main_r5fss1_core0_dma_memory_region>,
			<&main_r5fss1_core0_memory_region>;
};

&main_r5fss1_core1 {
	status = "okay";
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
	memory-region = <&main_r5fss1_core1_dma_memory_region>,
			<&main_r5fss1_core1_memory_region>;
};

&main_r5fss2_core0 {
	status = "okay";
	mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
	memory-region = <&main_r5fss2_core0_dma_memory_region>,
			<&main_r5fss2_core0_memory_region>;
};

&main_r5fss2_core1 {
	status = "okay";
	mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
	memory-region = <&main_r5fss2_core1_dma_memory_region>,
			<&main_r5fss2_core1_memory_region>;
};

&c71_0 {
	status = "okay";
	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
	memory-region = <&c71_0_dma_memory_region>,
			<&c71_0_memory_region>;
};

&c71_1 {
	status = "okay";
	mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
	memory-region = <&c71_1_dma_memory_region>,
			<&c71_1_memory_region>;
};

&c71_2 {
	status = "okay";
	mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
	memory-region = <&c71_2_dma_memory_region>,
			<&c71_2_memory_region>;
};

&c71_3 {
	status = "okay";
	mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
	memory-region = <&c71_3_dma_memory_region>,
			<&c71_3_memory_region>;
};

&dp0_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		dp0_in: endpoint {
			remote-endpoint = <&dpi0_out>;
		};
	};

	port@4 {
		reg = <4>;
		dp0_out: endpoint {
			remote-endpoint = <&dp0_connector_in>;
		};
	};
};

&ti_csi2rx0 {
	status = "okay";
	/* MIPI-CSI Connector 0 */
};

&ti_csi2rx1 {
	status = "okay";
	/* MIPI-CSI Connector 0 */
};

&ti_csi2rx2 {
	status = "okay";
	/* MIPI-CSI Connector 1 */
};

&dphy_rx0 {
	status = "okay";
};

&dphy_rx1 {
	status = "okay";
};

&dphy_rx2 {
	status = "okay";
};

&tscadc0 {
	pinctrl-0 = <&mcu_adc0_pins_default>;
	pinctrl-names = "default";
	status = "okay";
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&tscadc1 {
	pinctrl-0 = <&mcu_adc1_pins_default>;
	pinctrl-names = "default";
	status = "okay";
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&dphy_tx0 {
	status = "okay";
};

&dsi0 {
	status = "okay";
};

#define K3_TS_OFFSET(pa, val)  (0x4+(pa)*4) (0x10000 | val)

&timesync_router {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_cpts>;

	/* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */
	mcu_cpsw_cpts: mcu-cpsw-cpts {
		pinctrl-single,pins = <
			/* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */
			K3_TS_OFFSET(25, 17)
			>;
	};
};

&wkup_uart0 {
	status = "reserved";
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_uart0_pins_default>;
};

&mcu_uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_uart0_pins_default>;
};

&mcu_mcan0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_mcan0_pins_default>;
	phys = <&transceiver1>;
};

&mcu_mcan1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_mcan1_pins_default>;
	phys = <&transceiver2>;
};

&main_mcan16 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan16_pins_default>;
	phys = <&transceiver3>;
};

regards,

Prasad

Hi Prasad,

Couple of things to check: 

• The interrupt number for the uart instance.
• The Rx pad configuration. Is that configured as pin_input?

Regards,

Keerthy 

Hello Keerthy,

Yes all the needed configuration are done and this UART5 is working fine(Both Rx and Tx) in normal mode

but if i use this UART for debug console then only RX alone is not working only Tx is working.

changes i made  in k3-j784s4-evm.dts file.

chosen {
stdout-path = "serial2:115200n8";
};

aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart5;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
i2c0 = &main_i2c0;
};

main_uart5_pins_default: main_uart5-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x008, PIN_INPUT, 11) /* (AJ33) MCAN12_RX.UART5_RXD */
J784S4_IOPAD(0x004, PIN_OUTPUT, 11) /* (AG36) MCAN12_TX.UART5_TXD */
>;
};

Regards,

Prasad.

Hi Prasad,

Please share the complete boot logs as a text file attachment.

I need to check if UART5 gets probed correctly. The other thing to check if you have ethernet you can try telnet to your device and check if UART5 interrupts are registered correctly. 

Best Regards,

Keerthy 

Hello Keerthy,

I installed latest linux sdk version: ti-processor-sdk-linux-adas-j784s4-evm-09_02_00_05.

I followed the steps mentioned in the below link to configure wkup_uart0 for debug console for SPL boot. attached patch for reference.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1109996/faq-tda4vm-how-to-boot-using-wkup-uart

I copied images from below paths to sd card.

/home/sandra/latest-bsp/board-support/ti-u-boot-2023.04+gitAUTOINC+f9b966c674/build/a72/

tispl.bin_unsigned

u-boot.img_unsigned

/home/sandra/latest-bsp/board-support/ti-u-boot-2023.04+gitAUTOINC+f9b966c674/build/r5

tiboot3.bin

rebooted the board but nothing prints on the wkup_uart0 console. can you please replicate same on your end and provide me some break through here?

Note: with above changes only u-boot.img is adding prints on wkup_uart0. (this scenario I tested with sdk default tiboot3, tispl.bin and modified u-boot)

apart from above changes do we need to do any clock changes for wkup_uart0 in below files?

modified: arch/arm/mach-k3/j784s4/clk-data.c
modified: arch/arm/mach-k3/j784s4/dev-data.c

can you please try on your side configuring wkup_uart0 for console for tiboot3.bin and tispl.bin and u-boot? 

Regards,

Prasad.

From aeeefeabb46a7d8887aa9da45557dee2719bb689 Mon Sep 17 00:00:00 2001
From: Sandra RangaPrasad <rangaprasad.sandra@aptiv.com>
Date: Mon, 27 May 2024 16:58:16 +0530
Subject: [PATCH] wkup_uart0_debug-changes

---
 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 5 +++--
 arch/arm/dts/k3-j784s4-evm.dts         | 6 +++---
 arch/arm/dts/k3-j784s4-r5-evm.dts      | 2 +-
 board/ti/j784s4/j784s4.env             | 2 +-
 4 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
index 965aeed6..5f58ca93 100644
--- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -13,9 +13,9 @@
 
 	aliases {
 		ethernet0 = &mcu_cpsw_port1;
-		serial0 = &wkup_uart0;
+		serial0 = &main_uart8;
 		serial1 = &mcu_uart0;
-		serial2 = &main_uart8;
+		serial2 = &wkup_uart0;
 		i2c0 = &wkup_i2c0;
 		i2c1 = &mcu_i2c0;
 		i2c2 = &mcu_i2c1;
@@ -138,6 +138,7 @@
 
 &wkup_uart0 {
 	bootph-pre-ram;
+	status = "okay";
 };
 
 &main_sdhci0 {
diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts
index 539471c8..292ff67f 100644
--- a/arch/arm/dts/k3-j784s4-evm.dts
+++ b/arch/arm/dts/k3-j784s4-evm.dts
@@ -20,7 +20,7 @@
 	};
 
 	aliases {
-		serial2 = &main_uart8;
+		serial2 = &wkup_uart0;
 		mmc0 = &main_sdhci0;
 		mmc1 = &main_sdhci1;
 		i2c0 = &main_i2c0;
@@ -388,10 +388,10 @@
 	};
 };
 
-&main_uart8 {
+&wkup_uart0 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart8_pins_default>;
+	pinctrl-0 = <&wkup_uart0_pins_default>;
 };
 
 &main_i2c0 {
diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts
index 269f227f..6ddd42db 100644
--- a/arch/arm/dts/k3-j784s4-r5-evm.dts
+++ b/arch/arm/dts/k3-j784s4-r5-evm.dts
@@ -13,7 +13,7 @@
 / {
 	chosen {
 		firmware-loader = &fs_loader0;
-		stdout-path = &main_uart8;
+		stdout-path = &wkup_uart0;
 		tick-timer = &timer1;
 	};
 
diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
index 49772d89..b9e3ae0b 100644
--- a/board/ti/j784s4/j784s4.env
+++ b/board/ti/j784s4/j784s4.env
@@ -18,7 +18,7 @@ findfdt=
 	setenv fdtfile ${name_fdt}
 name_kern=Image
 console=ttyS2,115200n8
-args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02880000
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x42300000
 	${mtdparts}
 run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
 
-- 
2.34.1

Hi Prasad,

Let us first make sure that you are getting CCCCCCC on the WKUP_UART0.

I am using EVM. Dip switch settings:

SW2[1-8]  = 0xxx xxxx
SW11[1-8] = 0000 1000
SW7[1-8]  = 0111 0000

Please confirm if you are seeing this on WKUP_UART?

- Keerthy

Hi Keerthy,

yes I am seeing the data CCCC on wkup_uart0.

Regards,

Prasad.

Hi Prasad,

diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index f3a7519a..fb9abe83 100644
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -345,8 +345,8 @@
 			bucka1234: buck1234 {
 				bootph-pre-ram;
 				regulator-name = "vdd_cpu_avs";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <900000>;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
index 965aeed6..0cfe6ca7 100644
--- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -13,9 +13,9 @@
 
 	aliases {
 		ethernet0 = &mcu_cpsw_port1;
-		serial0 = &wkup_uart0;
+		serial2 = &wkup_uart0;
 		serial1 = &mcu_uart0;
-		serial2 = &main_uart8;
+		serial0 = &main_uart8;
 		i2c0 = &wkup_i2c0;
 		i2c1 = &mcu_i2c0;
 		i2c2 = &mcu_i2c1;
@@ -138,6 +138,7 @@
 
 &wkup_uart0 {
 	bootph-pre-ram;
+	status = "okay";
 };
 
 &main_sdhci0 {
diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts
index 539471c8..9d585415 100644
--- a/arch/arm/dts/k3-j784s4-evm.dts
+++ b/arch/arm/dts/k3-j784s4-evm.dts
@@ -20,7 +20,7 @@
 	};
 
 	aliases {
-		serial2 = &main_uart8;
+		serial2 = &wkup_uart0;
 		mmc0 = &main_sdhci0;
 		mmc1 = &main_sdhci1;
 		i2c0 = &main_i2c0;
@@ -293,6 +293,7 @@
 };
 
 &wkup_pmx2 {
+	bootph-pre-ram;
 	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
 		pinctrl-single,pins = <
 			J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
@@ -327,6 +328,7 @@
 	};
 
 	wkup_uart0_pins_default: wkup-uart0-pins-default {
+		bootph-pre-ram;
 		pinctrl-single,pins = <
 			J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_UART0_CTSn */
 			J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_UART0_RTSn */
@@ -388,10 +390,12 @@
 	};
 };
 
-&main_uart8 {
+&wkup_uart0 {
+	bootph-pre-ram;
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart8_pins_default>;
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+	clock-frequency = <96000000>;
 };
 
 &main_i2c0 {
diff --git a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
index ac63266e..e2d57569 100644
--- a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
@@ -114,10 +114,6 @@
 		reg = <0x00 0x42300000 0x00 0x200>;
 		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
 		current-speed = <115200>;
-		clocks = <&k3_clks 397 0>;
-		clock-names = "fclk";
-		power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
-		status = "disabled";
 	};
 
 	mcu_uart0: serial@40a00000 {
diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts
index 269f227f..6ddd42db 100644
--- a/arch/arm/dts/k3-j784s4-r5-evm.dts
+++ b/arch/arm/dts/k3-j784s4-r5-evm.dts
@@ -13,7 +13,7 @@
 / {
 	chosen {
 		firmware-loader = &fs_loader0;
-		stdout-path = &main_uart8;
+		stdout-path = &wkup_uart0;
 		tick-timer = &timer1;
 	};
 

Try with these changes and compile tiboot3.bin. You should see R5 SPL Prints.

Regards,
Keerthy

Hi Keerthy,

These changes will work only for tiboot3.bin? 

I made the changes as per your suggestion and only tiboot3.bin adding print on wkup_uart0 after that booting is stuck.

I used make u-boot command to build the images and used tiboot3.bin and tispl.bin_unsigned and u-boot.img_unsigned.

for you with above changes all the 3 images adding prints on wkup_uart0?

From a1d9b6e92e705aafc9ece4db8d908b8cd33e97ee Mon Sep 17 00:00:00 2001
From: Sandra RangaPrasad <rangaprasad.sandra@aptiv.com>
Date: Tue, 28 May 2024 14:11:28 +0530
Subject: [PATCH] ti-wakup-uart0-changes

---
 arch/arm/dts/k3-j721s2-r5-common-proc-board.dts | 4 ++--
 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi          | 5 +++--
 arch/arm/dts/k3-j784s4-evm.dts                  | 9 ++++++---
 arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi          | 4 ----
 arch/arm/dts/k3-j784s4-r5-evm.dts               | 2 +-
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index f3a7519a..fb9abe83 100644
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -345,8 +345,8 @@
 			bucka1234: buck1234 {
 				bootph-pre-ram;
 				regulator-name = "vdd_cpu_avs";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <900000>;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
index 965aeed6..5f58ca93 100644
--- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -13,9 +13,9 @@
 
 	aliases {
 		ethernet0 = &mcu_cpsw_port1;
-		serial0 = &wkup_uart0;
+		serial0 = &main_uart8;
 		serial1 = &mcu_uart0;
-		serial2 = &main_uart8;
+		serial2 = &wkup_uart0;
 		i2c0 = &wkup_i2c0;
 		i2c1 = &mcu_i2c0;
 		i2c2 = &mcu_i2c1;
@@ -138,6 +138,7 @@
 
 &wkup_uart0 {
 	bootph-pre-ram;
+	status = "okay";
 };
 
 &main_sdhci0 {
diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts
index 539471c8..581eb8db 100644
--- a/arch/arm/dts/k3-j784s4-evm.dts
+++ b/arch/arm/dts/k3-j784s4-evm.dts
@@ -20,7 +20,7 @@
 	};
 
 	aliases {
-		serial2 = &main_uart8;
+		serial2 = &wkup_uart0;
 		mmc0 = &main_sdhci0;
 		mmc1 = &main_sdhci1;
 		i2c0 = &main_i2c0;
@@ -293,6 +293,7 @@
 };
 
 &wkup_pmx2 {
+	bootph-pre-ram;
 	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
 		pinctrl-single,pins = <
 			J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
@@ -327,6 +328,7 @@
 	};
 
 	wkup_uart0_pins_default: wkup-uart0-pins-default {
+		bootph-pre-ram;
 		pinctrl-single,pins = <
 			J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_UART0_CTSn */
 			J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_UART0_RTSn */
@@ -388,10 +390,11 @@
 	};
 };
 
-&main_uart8 {
+&wkup_uart0 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart8_pins_default>;
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+	clock-frequency = <96000000>;
 };
 
 &main_i2c0 {
diff --git a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
index ac63266e..e2d57569 100644
--- a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
@@ -114,10 +114,6 @@
 		reg = <0x00 0x42300000 0x00 0x200>;
 		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
 		current-speed = <115200>;
-		clocks = <&k3_clks 397 0>;
-		clock-names = "fclk";
-		power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
-		status = "disabled";
 	};
 
 	mcu_uart0: serial@40a00000 {
diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts
index 269f227f..6ddd42db 100644
--- a/arch/arm/dts/k3-j784s4-r5-evm.dts
+++ b/arch/arm/dts/k3-j784s4-r5-evm.dts
@@ -13,7 +13,7 @@
 / {
 	chosen {
 		firmware-loader = &fs_loader0;
-		stdout-path = &main_uart8;
+		stdout-path = &wkup_uart0;
 		tick-timer = &timer1;
 	};
 
-- 
2.34.1

Regards,

Prasad.

Hello Keerthy,

I built the bl31.bin with below changes  in platfrom_def.h and copied bl31.bin to prebuilt directory. and rebuilt the images using make u-boot

#define K3_USART_BASE (0x42300000 + 0x10000 * K3_USART)

#define K3_USART_CLK_SPEED 96000000

with above changes I could see bl31 adding prints on the wkup_uart0. and stuck

Next image in the bootflow is OPTEE, for this i made the changes in below file

/home/sandra/latest-bsp/board-support/optee-os-4.1.0+gitAUTOINC+012cdca49d/core/arch/arm/plat-ti/platform_config.h.

#define K3_USART_BASE (0x42300000 + 0x10000 * K3_USART)

#define K3_USART_CLK_SPEED 96000000

how to rebuilt OPTEE image ? what is the command?

for OPTEE above change is sufficient ?

tiboot3 and bl31.bin adding print on wkup_uart0 as below.

Regards,

Prasad.

Hi Prasad,

Let us bypass OPTEE for now. Build ATF without "SPD=opteed"

This will ensure ATF directly loads A72 SPL and bypasses the OPTEEE.

- Keerthy

Hi Keerthy,

I built ATF with out opteed option and able to boot till u-boot.

now kernel booting is stuck.

U-Boot SPL 2023.04-00001-ga1d9b6e9 (May 28 2024 - 16:44:26 +0530)
ti_power_domain_probe(dev=41c661b8)
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
clk_register: faier: failed to get  device (parent of osc_26_mhz)
clk_register: failed to get  device (parent of osc_25_mhz)
clk_register: faiailed to get  device (parent of osc_20_mhz)
clk_register: failed to get  device (parent of osc_19_2_mhz)
clk_register: failedegister: failed to get  device (parent of board_0_mcu_ospi0_dqs_out)
clk_register: failed to get  device (parent of board_0_mcent of board_0_wkup_i2c0_scl_out)
clk_register: failed to get  device (parent of fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n)
clk_rus1p0_0_hpb_out_clk_p)
clk_register: failed to get  device (parent of fss_mcu_0_ospi_0_ospi_oclk_clk)
clk_register: failed toclk_register: failed to get  device (parent of j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk)
clk_register: failed to get  devi
                                 clk_register: failed to get  device (parent of mshsi2c_wkup_0_porscl)
clk_register: failed to get  device (parent of board_0_register: failed to get  device (parent of board_0_ext_refclk1_out)
clk_register: failed to get  device (parent of board_0_mcu(parent of board_0_mcu_ext_refclk0_out)
clk_register: failed to get  device (parent of board_0_mmc1_clklb_out)
clk_register: k_register: failed to get  device (parent of board_0_tck_out)
clk_register: failed to get  device (parent of board_0_vout0_extof emmcsd4ss_main_0_emmcsdss_io_clk_o)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
SPL initial stack usage: 13456 bytes
Trying to boot from MMC2
Loading Environment from nowhere... OK
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.10.0(release):v2.10.0-367-g00f1ec6b8-dirty
NOTICE:  BL31: Built : 16:42:20,
U-Boot SPL 2023.04-00001-ga1d9b6e9 (May 28 2024 - 16:44:15 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
Trying to boot from MMC2


U-Boot 2023.04-00001-ga1d9SoC:   J784S4 SR1.0 GP
Model: Texas Instruments J784S4 EVM
Board: J784S4X-EVM rev E4
DRAM:  2 GiB (effective 32 GiB)
idle-statesCore:  91 devices, 32 uclasses, devicetree: separate
Flash: 0 Bytes
MMC:   mmc@4f80000: 0, mmc@4fb0000: 1
Loading Environment from nowhere... OK
In:    serial@42300000
Out:   serial@42300000
Err:   serial@42300000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_verHit any key to stop autoboot:  0 
switch to partitions #0, OK
mmc1 is current device
SD/MMC found on device 1
574 bytes read in 24 ms (22.5 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc1 ...
gpio: pin gpio@22_17 (gpio 188) value is 1
gpio: pin gpio@22_16 (k3_r5f_rproc r5f@41000000: Core 1 is already in use. No rproc commands work
Failed to load '/lib/firmware/j784s4-mcu-r5f0_1-fw'
Failed to load '/lib/firmware/j784s4-main-r5f0_0-fw'
Failed to load '/lib/firmware/j784s4-main-r5f0_1-fw'
Failed to load '/lib/firmware/j784s4-main-r5f1_0-fw'
Failed to load '/lib/firmware/j784s4-main-r5f1_1-fw'
Failed to load '/lib/firmware/j784s4-main-r5f2_0-fw'
Failed to load '/lib/firmware/j784s4-main-r5f2_1-fw'
Failed to load '/lib/firmware/j784s4-c71_0-fw'
Failed to load '/lib/firmware/j784s4-c71_1-fw'
Failed to load '/lib/firmware/j784s4-c71_2-fw'
Failed to load '/lib/firmware/j784s4-c71_3-fw'
19378688 bytes read in 248 ms (74.5 MiB/s)
114407 bytes read in 27 ms (4 MiB/s)
Working FDT set to 88000000
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x8800   Loading Device Tree to 000000008fee1000, end 000000008fffffff ... OK
Working FDT set to 8fee1000

Starting kernel ...

Regards,

Prasad.

Hi Prasad,

You will need to change the console parameter similar to U-Boot.

Best Regards,

Keerthy 

Hi Keerthy,

I already had the changes for linux in k3-j784s4-evm.dts file.

booting is stuck immediately after u-boot.

I believe its because of tiboot3 and tispl.bin changes, because previously u-boot and linux was working on wkup_uart0. 

From a4a361ee79e4a11a9e04616de8abd2f293c06f68 Mon Sep 17 00:00:00 2001
From: Sandra RangaPrasad <rangaprasad.sandra@aptiv.com>
Date: Wed, 29 May 2024 11:43:03 +0530
Subject: [PATCH] wkup-uart0-dts-linux

---
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts      | 41 +++++++++++++++++--
 .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi     |  4 --
 2 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 0c1fd77fc..0a31204d1 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -20,9 +20,9 @@ chosen {
 	};
 
 	aliases {
-		serial0 = &wkup_uart0;
+		serial0 = &main_uart5;
 		serial1 = &mcu_uart0;
-		serial2 = &main_uart8;
+		serial2 = &wkup_uart0;
 		mmc0 = &main_sdhci0;
 		mmc1 = &main_sdhci1;
 		i2c0 = &main_i2c0;
@@ -387,11 +387,15 @@ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) MCU_UART0_TXD */
 	};
 
 	wkup_uart0_pins_default: wkup-uart0-pins-default {
 		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_UART0_CTSn */
+			J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_UART0_RTSn */
 			J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
 			J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */
 		>;
 	};
+
 	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
 		pinctrl-single,pins = <
 			J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
@@ -572,6 +576,22 @@ J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */
 		>;
 	};
 
+    	main_uart3_pins_default: main_uart3-default-pins {
+        	pinctrl-single,pins = <
+            		J784S4_IOPAD(0x074, PIN_INPUT, 11) /* (AC33) MCAN2_TX.UART3_RXD */
+            		J784S4_IOPAD(0x078, PIN_INPUT, 11) /* (AH37) MCAN2_RX.UART3_TXD */
+        	>;
+    	};
+    	
+    main_uart5_pins_default: main-uart5-pins-default {
+        pinctrl-single,pins = <
+            J784S4_IOPAD(0x0a4, PIN_INPUT, 11) /* (AJ36) MCASP0_AXR13.UART5_CTSn */
+            J784S4_IOPAD(0x0a8, PIN_OUTPUT, 11) /* (AF34) MCASP0_AXR14.UART5_RTSn */
+            J784S4_IOPAD(0x09c, PIN_INPUT, 11) /* (AF35) MCASP0_AXR11.UART5_RXD */
+            J784S4_IOPAD(0x0a0, PIN_OUTPUT, 11) /* (AD34) MCASP0_AXR12.UART5_TXD */
+        >;
+    };
+    
 	main_uart8_pins_default: main-uart8-pins-default {
 		pinctrl-single,pins = <
 			J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
@@ -693,9 +713,21 @@ J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */
 	};
 };
 
-&main_uart8 {
+&main_uart3 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart3_pins_default>;
+};
+
+&main_uart5 {
 	status = "okay";
 	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart5_pins_default>;
+};
+
+&main_uart8 {
+	status = "disabled";
+	pinctrl-names = "default";
 	pinctrl-0 = <&main_uart8_pins_default>;
 };
 
@@ -1499,9 +1531,10 @@ K3_TS_OFFSET(25, 17)
 };
 
 &wkup_uart0 {
-	status = "reserved";
+	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wkup_uart0_pins_default>;
+	clock-frequency = <96000000>;
 };
 
 &mcu_uart0 {
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index 4f6b97745..a69e6143c 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -114,10 +114,6 @@ wkup_uart0: serial@42300000 {
 		reg = <0x00 0x42300000 0x00 0x200>;
 		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
 		current-speed = <115200>;
-		clocks = <&k3_clks 397 0>;
-		clock-names = "fclk";
-		power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
-		status = "disabled";
 	};
 
 	mcu_uart0: serial@40a00000 {
-- 
2.34.1

Regards,

Prasad.

Hi prasad,

diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 423cf546..3ac1e9e3 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -14,8 +14,8 @@
 
 / {
 	chosen {
-		stdout-path = "serial2:115200n8";
-		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+		stdout-path = "serial1:115200n8";
+		bootargs = "console=ttyS1,115200n8 earlycon=ns16550a,mmio32,0x40a00000";
 	};

Have you tried similar change in the bootargs in the U-Boot? This typically gets the earlyconsole from there. Let me know if similar change helps for J784s4?

- Keerthy

Hi Keerthy,

I modified j784s4.env file for wakup_uart0 base address.

now I could see the kernel logs on wakup_uart0.

I would like to understand below regulator change in k3-j721s2-r5-common-proc-board.dts, can you please explain why we need below change?

this will affect only wkup_uart0 lines ?

diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
index f3a7519a..fb9abe83 100644
--- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -345,8 +345,8 @@
bucka1234: buck1234 {
bootph-pre-ram;
regulator-name = "vdd_cpu_avs";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <900000>;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};

Regards,

Prasad.

Hi Keerthy,

Sure  will Create the patch and I will Attach.

one more query, we have deleted clock and power domain for wakup_uart0, in this case which clock and power domain will be used for wkup_uart0?

diff --git a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
index ac63266e..e2d57569 100644
--- a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
@@ -114,10 +114,6 @@
reg = <0x00 0x42300000 0x00 0x200>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
- clocks = <&k3_clks 397 0>;
- clock-names = "fclk";
- power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
};

Regards,

Prasad.

Hi Keerthy,

Thanks for the clarification.

ATF patch for wkup_uart0

From 42f38248f75d52afb3e1517740577ab4b3afd08f Mon Sep 17 00:00:00 2001
From: Sandra RangaPrasad <rangaprasad.sandra@aptiv.com>
Date: Thu, 30 May 2024 14:22:36 +0530
Subject: [PATCH] wkup-uart0-for-debug-console

---
 plat/ti/k3/include/platform_def.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h
index a2cc62d34..d008169c5 100644
--- a/plat/ti/k3/include/platform_def.h
+++ b/plat/ti/k3/include/platform_def.h
@@ -105,14 +105,14 @@
 
 /* Platform default console definitions */
 #ifndef K3_USART_BASE
-#define K3_USART_BASE			(0x02800000 + 0x10000 * K3_USART)
+#define K3_USART_BASE			(0x42300000 + 0x10000 * K3_USART)
 #endif
 
 /* USART has a default size for address space */
 #define K3_USART_SIZE 0x1000
 
 #ifndef K3_USART_CLK_SPEED
-#define K3_USART_CLK_SPEED 48000000
+#define K3_USART_CLK_SPEED 96000000
 #endif
 
 /* Crash console defaults */
-- 
2.34.1

u-boot patch for wkup_uart0

From a1d9b6e92e705aafc9ece4db8d908b8cd33e97ee Mon Sep 17 00:00:00 2001
From: Sandra RangaPrasad <rangaprasad.sandra@aptiv.com>
Date: Tue, 28 May 2024 14:11:28 +0530
Subject: [PATCH] ti-wakup-uart0-changes

---
 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi          | 5 +++--
 arch/arm/dts/k3-j784s4-evm.dts                  | 9 ++++++---
 arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi          | 4 ----
 arch/arm/dts/k3-j784s4-r5-evm.dts               | 2 +-
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
index 965aeed6..5f58ca93 100644
--- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -13,9 +13,9 @@
 
 	aliases {
 		ethernet0 = &mcu_cpsw_port1;
-		serial0 = &wkup_uart0;
+		serial0 = &main_uart8;
 		serial1 = &mcu_uart0;
-		serial2 = &main_uart8;
+		serial2 = &wkup_uart0;
 		i2c0 = &wkup_i2c0;
 		i2c1 = &mcu_i2c0;
 		i2c2 = &mcu_i2c1;
@@ -138,6 +138,7 @@
 
 &wkup_uart0 {
 	bootph-pre-ram;
+	status = "okay";
 };
 
 &main_sdhci0 {
diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts
index 539471c8..581eb8db 100644
--- a/arch/arm/dts/k3-j784s4-evm.dts
+++ b/arch/arm/dts/k3-j784s4-evm.dts
@@ -20,7 +20,7 @@
 	};
 
 	aliases {
-		serial2 = &main_uart8;
+		serial2 = &wkup_uart0;
 		mmc0 = &main_sdhci0;
 		mmc1 = &main_sdhci1;
 		i2c0 = &main_i2c0;
@@ -293,6 +293,7 @@
 };
 
 &wkup_pmx2 {
+	bootph-pre-ram;
 	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
 		pinctrl-single,pins = <
 			J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
@@ -327,6 +328,7 @@
 	};
 
 	wkup_uart0_pins_default: wkup-uart0-pins-default {
+		bootph-pre-ram;
 		pinctrl-single,pins = <
 			J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_UART0_CTSn */
 			J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_UART0_RTSn */
@@ -388,10 +390,11 @@
 	};
 };
 
-&main_uart8 {
+&wkup_uart0 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart8_pins_default>;
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+	clock-frequency = <96000000>;
 };
 
 &main_i2c0 {
diff --git a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
index ac63266e..e2d57569 100644
--- a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
@@ -114,10 +114,6 @@
 		reg = <0x00 0x42300000 0x00 0x200>;
 		interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
 		current-speed = <115200>;
-		clocks = <&k3_clks 397 0>;
-		clock-names = "fclk";
-		power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
-		status = "disabled";
 	};
 
 	mcu_uart0: serial@40a00000 {
diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts
index 269f227f..6ddd42db 100644
--- a/arch/arm/dts/k3-j784s4-r5-evm.dts
+++ b/arch/arm/dts/k3-j784s4-r5-evm.dts
@@ -13,7 +13,7 @@
 / {
 	chosen {
 		firmware-loader = &fs_loader0;
-		stdout-path = &main_uart8;
+		stdout-path = &wkup_uart0;
 		tick-timer = &timer1;
 	};
 
-- 
2.34.1

From b5ce3688a009261e9e88c6bb46493c78804bdad3 Mon Sep 17 00:00:00 2001
From: Sandra RangaPrasad <rangaprasad.sandra@aptiv.com>
Date: Thu, 30 May 2024 12:11:27 +0530
Subject: [PATCH] wkup-uart0-uenv-change

---
 board/ti/j784s4/j784s4.env | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
index 49772d89..b9e3ae0b 100644
--- a/board/ti/j784s4/j784s4.env
+++ b/board/ti/j784s4/j784s4.env
@@ -18,7 +18,7 @@ findfdt=
 	setenv fdtfile ${name_fdt}
 name_kern=Image
 console=ttyS2,115200n8
-args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02880000
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x42300000
 	${mtdparts}
 run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
 
-- 
2.34.1

Regards,

Prasad.

Hi Keerthy,

how to bypass OPTEE image in yoctobuild environment ?

I am trying to apply the wkup_uart0 patches in yoctobuild and i used below command to build the images.

MACHINE="j784s4-evm" bitbake tisdk-tiny-image

OPTEE image(bl32) is included in Bl31 .bin with above command. can you please help with command to bypass the OPTEE image in yoctobuild?

Regards,

Prasad.

Hi Keerthy,

Thanks, raised new ticket for yocto support.

PROCESSOR-SDK-J784S4: Bypass OPTEE Image in tispl.bin - Processors forum - Processors - TI E2E support forums

I have another query regarding OPTEE(BL32) image.

what is the impact of bypassing OPTEE image in case of secure boot?

with out BL32 secure boot will still work? what is the main use case of OP-TEE?

Regards,

Prasad.

prasad sandra said:

with out BL32 secure boot will still work? what is the main use case of OP-TEE?

Yes. That has no dependency on Secure boot. If you need OPTEE then we can enable a patch to change console in OPTEE as well.
Let me know.

- Keerthy

Hi Keerthy,

Thanks for the reply!!!.

Yes I need the patch for OPTEE also, can you please provide patch and the instructions on how to build ?

Regards,

Prasad.

Hello Keerthy,

We don't package the OPTEE source code. So you will need to clone:

I could see, there is OPTEE source code as part of sdk board-support package.

home/sandra/latest-bsp/board-support/optee-os-4.1.0+gitAUTOINC+012cdca49d

installed gcc tool chain using below command

sudo apt-get install  gcc-arm*

OPTEE changes patch as below.

I rebuilt the OPTEE source and ATF with SPD=opteed option as below.

OPTEE:
make PLATFORM=k3-j784s4 CFG_ARM64_core=y

ATF:
make CROSS_COMPILE=/home/sandra/ti/arm-gnu-toolchain-11.3.rel1-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed

after that I copied BL31.bin to prebuilt folder and rebuilt the u-boot(make u-boot)
copied images to sd card, booting is stuck after BL31

how to integrate BL32(OPTEE) into Bl31 or tispl.bin ? SPD=opteed option does this?

boot log.
U-Boot SPL 2023.04-dirty (Jun 17 2024 - 17:01:26 +0530)
ti_power_domain_probe(dev=41c661b8)
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
ti_i2c_eeprom_am6_get: Ignoring record id 255
clk_register: failed to get  device (parent of osc_27_mhz)
clk_register: failed to get  device (parent of osc_26_mhz)
clk_register: failed to get  device (parent of osc_25_mhz)
clk_register: failed to get  device (parent of osc_24_mhz)
clk_register: failed to get  device (parent of osc_20_mhz)
clk_register: failed to get  device (parent of osc_19_2_mhz)
clk_register: failed to get  device (parent of board_0_hfosc1_clk_out)
clk_register: failed to get  device (parent of board_0_mcu_ospi0_dqs_out)
clk_register: failed to get  device (parent of board_0_mcu_ospi1_dqs_out)
clk_register: failed to get  device (parent of board_0_wkup_i2c0_scl_out)
clk_register: failed to get  device (parent of fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n)
clk_register: failed to get  device (parent of fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p)
clk_register: failed to get  device (parent of fss_mcu_0_ospi_0_ospi_oclk_clk)
clk_register: failed to get  device (parent of fss_mcu_0_ospi_1_ospi_oclk_clk)
clk_register: failed to get  device (parent of j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk)
clk_register: failed to get  device (parent of j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk)
clk_register: failed to get  device (parent of mshsi2c_wkup_0_porscl)
clk_register: failed to get  device (parent of board_0_cpts0_rft_clk_out)
clk_register: failed to get  device (parent of board_0_ext_refclk1_out)
clk_register: failed to get  device (parent of board_0_mcu_cpts0_rft_clk_out)
clk_register: failed to get  device (parent of board_0_mcu_ext_refclk0_out)
clk_register: failed to get  device (parent of board_0_mmc1_clklb_out)
clk_register: failed to get  device (parent of board_0_mmc1_clk_out)
clk_register: failed to get  device (parent of board_0_tck_out)
clk_register: failed to get  device (parent of board_0_vout0_extpclkin_out)
clk_register: failed to get  device (parent of emmcsd4ss_main_0_emmcsdss_io_clk_o)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.4--v09.02.04 (Kool Koala)')
SPL initial stack usage: 13456 bytes
Trying to boot from MMC2
Loading Environment from nowhere... OK
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.10.0(release):v2.10.0-503-g27b0440a8-dirty
NOTICE:  BL31: Built : 16:58:56, Jun 17 2024


ATF patch.

From ef00258f7793933124a49dfa98aa01f51b59fb0a Mon Sep 17 00:00:00 2001
From: Sandra RangaPrasad <rangaprasad.sandra@aptiv.com>
Date: Mon, 17 Jun 2024 11:23:15 +0530
Subject: [PATCH] optee-wkup-uart0-changes

---
 core/arch/arm/plat-k3/platform_config.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/core/arch/arm/plat-k3/platform_config.h b/core/arch/arm/plat-k3/platform_config.h
index cffca0a07..937184c47 100644
--- a/core/arch/arm/plat-k3/platform_config.h
+++ b/core/arch/arm/plat-k3/platform_config.h
@@ -9,11 +9,11 @@
 
 #include <mm/generic_ram_layout.h>
 
-#define UART0_BASE      0x02800000
+#define UART0_BASE      0x42300000
 
 #define CONSOLE_UART_BASE       (UART0_BASE + CFG_CONSOLE_UART * 0x10000)
 #define CONSOLE_BAUDRATE        115200
-#define CONSOLE_UART_CLK_IN_HZ  48000000
+#define CONSOLE_UART_CLK_IN_HZ  96000000
 
 #define DRAM0_BASE      0x80000000
 #define DRAM0_SIZE      0x80000000
-- 
2.34.1

Regards,

Prasad.

prasad sandra said:

how to integrate BL32(OPTEE) into Bl31 or tispl.bin ? SPD=opteed option does this?

Go to the 

home/sandra/latest-bsp/board-support/optee-os-4.1.0+gitAUTOINC+012cdca49d

folder.

make PLATFORM=k3-j784s4 CFG_ARM64_core=y

Then copy the generated bl32.bin to prebuilt folder and then execute: make u-boot.

- Keerthy