can decoupling capacitors be replaced by capacitor arrays?

The end result of any PDN (power distribution network) should be that the total amount of capacitance required be present with the least possible amount of inductance. 

The capacitance required for Netra is in the data sheet, so as long as the array inductance is low, compared to placing separate capacitors, I would think this is fine.  For bypass capacitors, there are many solutions that will work.

For more information, see my Wiki on bypass capacitors:

http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design/BGA_decoupling#Methods_of_placement

Hi Keven,

I am designing a DM365 board and want to implement your idea of via sharing and placing escape vias for power on every other row per your wiki. Do you have drawings to illustrate what you mean? Do you mean that there will be only a single escape via for a pair of power balls on two adjacent rows so as to free space on the print side of the board to place the caps? If you have an Allegro file to illustrate this it would be great.

Thanks

Michael Hallak-Stamler

Michael,

> Do you mean that there will be only a single escape via for a pair of power balls on two adjacent rows so as to free space on the print side of the board to place the caps?

That is what I'm saying.  Processor chips rarely require a via for every power ball (maybe some super high speed application specific processors filled with high speed interfaces, but not the kind we sell the general public). 

Technically it would be best to have a via for every ball, but if you put the placement of the bypass capacitors into the equation, you'll realize that at ~8400nH/inch, it doesn't take much trace length to make a bypass capacitor mostly useless. 

The bypass caps really need to be placed as close as possible to the balls, and if you've got to share a few vias to get room underneath the part, that's a better solution because the increased inductance of one via over two is not that much in comparison to the extra inductance of long traces to the bypass capacitors.

There is a layout for the 814x on this Wiki that illustrates this point:

http://processors.wiki.ti.com/index.php/AM387x_/_C6A814x_PCB_Layout_guide

Just for reference for the other viewers who didn't see my Wiki on decoupling, here it is:

http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design/BGA_decoupling#General_number_and_value_of_capacitors_required

I hope I've answered your question.  Let me know if you have any more questions.  I'm happy to help.

Keven