Part Number: AM69
Other Parts Discussed in Thread: TDA4VH,
I want to compare TI test data vs customer test data.
There is not header of each colum, how to interpret the data?

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Hi,
The assigned engineer is on business travel till Apr-18. Please expect a delay in response till then
Regards,
Parth
Hi Tony,
Thanks for letting us know about this. It seems the SDK doc has some issues for 9.2 version. Please reference the 9.1 SDK docs for the headers: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j784s4/09_01_00_06/exports/docs/devices/J7_Family/linux/Release_Specific_Performance_Guide.html
I will open up an internal ticket to fix the header issue. At the latest, it should be fixed in next release.
Regards,
Takuma
Hi Takuma,
I did not find TDA4VH/J784s4 PCIe benchmark data on SDK9.1 user guide. Can you help to provide it?
Hi Tony,
I've got some numbers from 8.6 SDK, which should be similar to 9.1 SDK numbers.
For a total of around 4GB/s for 6 lanes being used simultaneously. These were ran using a PCIe NVMe device with the command: fio --name=/run/media/nvme0n1/test-pcie-1 --size=10GB --ioengine=libaio --iodepth=4 --numjobs=1 --direct=1 --runtime=60 --time_based --bs=4M
Feel free to run this on your end or at the customer end to confirm numbers.
Regards,
Takuma
Hi Takuma,
do you mean you tested with SDK8.6 on TDA4VH-EVM? or data from SDk8.6 user guide?
Is there method/guide to test between two TDA4 board?
Can I understand the efficiency of 4 Lane is : 2421MB * 8 /4x8Gbps=2.421*8/32=60.525%?
Where is the code of test-pcie-1?
Hi Tony,
Yes, I have tested with SDK 8.6 on TDA4VH-EVM and this was between a TDA4VH-EVM communicating to NVMe SSD card connected via PCIe. The "fio" commandline tool is installed in default Linux SDK image and test-pcie-1 is simply the name of the file the fio is writing to nvme0n1 SSD card.
8Gbps is theoretical throughput, but practical efficiency is affected by overhead from additional header required by packets, DMA initialization, and packet size.
Regards,
Takuma
Hi Takuma,
Customer setup 4Land PCIe test as the picture.

Got result <40% of PCIe3.0 max bandwidth
host -> device :1.5GB/s
device -> host :1.9GB/s
while test PCIe M.2 M key 2lane,got 50%~60% of PCIe3.0 max bandwidth
host->device: 1151 M/s
device->host: 1040 M/s
The 4Lane throughput is quite low, is it related to the physical connection? or software configuration? How can we know if it works in PCIe3.0, and 4 Lane mode already?
Hi Tony,
You can confirm how many lanes and what PCIe gen speed is being used by running /usr/sbin/lspci -vvv. This prints out the most verbose information about the PCIe connection. There should be a field that says how many lanes and speed each link is.
Regards,
Takuma