TDA4VM: DSI settings issue

Part Number: TDA4VM

Hello together,

we are trying to test the DSI output on the TDA4VM processor, unfortunately at some resolutions we don't see any output signal, for example at 1280x720. Could you please advise us which parameter is necessary to change?

TVG generator is working without any issue. DSI signal is stable in that case.
But when we try to use DPI output from DSS as the source of signal for DSI data line stays in IDLE state.
Continuous clock is stable at correct frequency.
We have tested several other DSI ref. clock frequencies without success.

Then we have tried several other resolutions and some of them are working and some not.
No error was detected by the driver. We are not found any rule what is behind that, just
some resolutions are working while other not. (examples are at the end of this report)

Workaround:
We have applied the patch for exact clock setting - drivers/clk/keystone/sci-clk.c
We have applied the patch "Wait time for Calibrations enable after bandgap is enabled" - drivers/phy/cadence/cdns-dphy.c

We have updated drivers/phy/cadence/cdns-dphy.c driver to allow set arbitrary reference clock using as source
the output from main PLL_3 HSDIVOUT4. Also we have tested that with fixed ref-clk 19.2Mhz and 24Mhz


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*************************************************************************************************************************************
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Mode definition:

&lvdspanel {
    panel-timing {
        clock-frequency = <74250000>;
        hactive = <1280>;
        vactive = <720>;
        hsync-len = <40>;    
        hfront-porch = <262>;
        hback-porch = <70>;  
        vsync-len = <5>;
        vfront-porch = <5>;
        vback-porch = <20>;
    };
};

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DSS and DSI setting:

&dphy2 {
    status = "okay";
#ifdef DSI_ON_MAIN3_HSDIV4
    /delete-property/ assigned-clocks;        
    /delete-property/ assigned-clock-parents;        
    /delete-property/ assigned-clock-rates;        
    assigned-clocks = <&k3_clks 296 3>;
    assigned-clock-parents = <&k3_clks 296 6>;
    assigned-clock-rates = <19200000>;
#else
    /delete-property/ assigned-clock-rates;        
    assigned-clock-rates = <24000000>; // sysclk OSC
#endif
};

&dsi0 {
    status = "okay";
};

&dss {
    status = "okay";
    /*
     * These clock assignments are chosen to enable the following outputs:
     *
     * VP0 - DisplayPort SST
     * VP1 - DPI0
     * VP2 - DSI
     * VP3 - DPI1
     */

    assigned-clocks = <&k3_clks 152 1>,
              <&k3_clks 152 4>,
              <&k3_clks 152 9>,
              <&k3_clks 152 13>;
    assigned-clock-parents = <&k3_clks 152 2>,    /* PLL16_HSDIV0 */
                 <&k3_clks 152 6>,    /* PLL19_HSDIV0 */
                 <&k3_clks 152 11>,    /* PLL18_HSDIV0 */
                 <&k3_clks 152 18>;    /* PLL23_HSDIV0 */
};

&dss_ports {
    .....
};

&dsi0_ports {
    .....
};


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*************************************************************************************************************************************
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HW State:

we have checked the state of hardware by reading registers but
only reported hardware status is:

DSI_VID_MODE_STS_FLAG:
root@j721e-cgtst4m:~# devmem2 0x4800180
/dev/mem opened.
Memory mapped at address 0xffff93c84000.
Read at address  0x04800180 (0xffff93c84180): 0x00000005

bits ERR_MISSING_HSYNC_FLAG and VSG_STS_FLAG are set

It looks that there is some effort to fill DSI FIFO

DSI_DPI_CFG:
root@j721e-cgtst4m:~# devmem2 0x48001ac
/dev/mem opened.
Memory mapped at address 0xffffb9048000.
Read at address  0x048001AC (0xffffb90481ac): 0x08000004
root@j721e-cgtst4m:~# devmem2 0x48001ac
/dev/mem opened.
Memory mapped at address 0xffff80cbb000.
Read at address  0x048001AC (0xffff80cbb1ac): 0x08000003

bit DPI_CFG_FIFO_LEVEL changes but values are from 0 up to 8


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*************************************************************************************************************************************
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DRIVER LOG:

Driver log was enhanced to see current setting:

DSI size parameters:

[    6.861946] cdns-dsi 4800000.dsi: cdns_dsi_bridge_enable: HFP = 780
[    6.861951] cdns-dsi 4800000.dsi: cdns_dsi_bridge_enable: HSA = 106
[    6.861955] cdns-dsi 4800000.dsi: cdns_dsi_bridge_enable: HBP = 198
[    6.861959] cdns-dsi 4800000.dsi: cdns_dsi_bridge_enable: HACT = 3840
[    6.861964] cdns-dsi 4800000.dsi: cdns_dsi_bridge_enable: HTOTAL = 4956
[    6.861968] cdns-dsi 4800000.dsi: cdns_dsi_bridge_enable: VFP = 5
[    6.861972] cdns-dsi 4800000.dsi: cdns_dsi_bridge_enable: VSA = 6
[    6.861976] cdns-dsi 4800000.dsi: cdns_dsi_bridge_enable: VBP = 19
[    6.861980] cdns-dsi 4800000.dsi: cdns_dsi_bridge_enable: VACT = 720

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DPHY PLL setting:

[    8.886544] phy phy-4480000.phy.14: cdns_dphy_config_from_opts: Phy Config VALID
[    8.886550] phy phy-4480000.phy.14: cdns_dsi_get_dphy_pll_cfg: ref clk is - 44550000
[    8.886574] phy phy-4480000.phy.14: cdns_dsi_get_dphy_pll_cfg: hs clk is - 445500000
[    8.886579] phy phy-4480000.phy.14: cdns_dsi_get_dphy_pll_cfg:  PLL SETUP:
[    8.886583] phy phy-4480000.phy.14: cdns_dsi_get_dphy_pll_cfg: ipdiv = 4
[    8.886587] phy phy-4480000.phy.14: cdns_dsi_get_dphy_pll_cfg: opdiv = 4
[    8.886592] phy phy-4480000.phy.14: cdns_dsi_get_dphy_pll_cfg: fbdiv = 320

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*************************************************************************************************************************************
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System PLL settings:  

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DPHY:

it is connected to <296 6> => DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK

root@j721e-cgtst4m:~# k3conf dump clock 296
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.2--v09.01.02 (Kool Koala))') |
|------------------------------------------------------------------------------|

|-------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                         | Status          | Clock Frequency |
|-------------------------------------------------------------------------------------------------------------------------------|
|   296     |     0    | DEV_DPHY_TX0_CLK                                                   | CLK_STATE_READY | 125000000       |
|   296     |     1    | DEV_DPHY_TX0_PSM_CLK                                               | CLK_STATE_READY | 20000000        |
|   296     |     2    | DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK                                | CLK_STATE_READY | 20000000        |
|   296     |     3    | DEV_DPHY_TX0_DPHY_REF_CLK                                          | CLK_STATE_READY | 44550000        |
|   296     |     4    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 24000000        |
|   296     |     5    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
|   296     |     6    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 44550000        |
|   296     |     7    | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
|   296     |     8    | DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK                            | CLK_STATE_READY | 0               |
|   296     |     9    | DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK                                | CLK_STATE_READY | 0               |
|   296     |    10    | DEV_DPHY_TX0_CK_P                                                  | CLK_STATE_READY | 0               |
|   296     |    11    | DEV_DPHY_TX0_CK_M                                                  | CLK_STATE_READY | 0               |
|   296     |    12    | DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK                            | CLK_STATE_READY | 0               |
|-------------------------------------------------------------------------------------------------------------------------------|

-------------------------------------------------------------------------------------------------------------------------------------
DSI core

root@j721e-cgtst4m:~# k3conf dump clock 150
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.2--v09.01.02 (Kool Koala))') |
|------------------------------------------------------------------------------|

|--------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                            | Status          | Clock Frequency |
|--------------------------------------------------------------------------------------------------|
|   150     |     0    | DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK        | CLK_STATE_READY | 0               |
|   150     |     1    | DEV_DSS_DSI0_DPI_0_CLK                | CLK_STATE_READY | 0               |
|   150     |     2    | DEV_DSS_DSI0_PLL_CTRL_CLK             | CLK_STATE_READY | 500000000       |
|   150     |     3    | DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0               |
|   150     |     4    | DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK        | CLK_STATE_READY | 20000000        |
|   150     |     5    | DEV_DSS_DSI0_SYS_CLK                  | CLK_STATE_READY | 250000000       |
|--------------------------------------------------------------------------------------------------|

-------------------------------------------------------------------------------------------------------------------------------------
TIDSS

root@j721e-cgtst4m:~# k3conf dump clock 152
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Fri Oct 06 12:20:16 UTC 2023)              |
| SoC    | J721E SR1.1                                                         |
| SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.1.2--v09.01.02 (Kool Koala))') |
|------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                                   | Status          | Clock Frequency |
|-----------------------------------------------------------------------------------------------------------------------------------------|
|   152     |     0    | DEV_DSS0_DSS_FUNC_CLK                                                        | CLK_STATE_READY | 600000000       |
|   152     |     1    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK                                           | CLK_STATE_READY | 600000000       |
|   152     |     2    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000       |
|   152     |     3    | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0                | CLK_STATE_READY | 600000000       |
|   152     |     4    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK                                           | CLK_STATE_READY | 600000000       |
|   152     |     5    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000       |
|   152     |     6    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0               | CLK_STATE_READY | 600000000       |
|   152     |     7    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0               | CLK_STATE_READY | 600000000       |
|   152     |     8    | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000       |
|   152     |     9    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK                                           | CLK_STATE_READY | 74250000        |
|   152     |    10    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000       |
|   152     |    11    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK | CLK_STATE_READY | 74250000        |
|   152     |    12    | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0               | CLK_STATE_READY | 600000000       |
|   152     |    13    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK                                           | CLK_STATE_READY | 600000000       |
|   152     |    14    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK | CLK_STATE_READY | 600000000       |
|   152     |    15    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK | CLK_STATE_READY | 600000000       |
|   152     |    16    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK | CLK_STATE_READY | 1188000000      |
|   152     |    17    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0               | CLK_STATE_READY | 600000000       |
|   152     |    18    | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0               | CLK_STATE_READY | 600000000       |
|   152     |    23    | DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK                                             | CLK_STATE_READY | 0               |
|   152     |    24    | DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK                                          | CLK_STATE_READY | 0               |
|   152     |    25    | DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK                                             | CLK_STATE_READY | 0               |
|   152     |    27    | DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK                                             | CLK_STATE_READY | 0               |
|   152     |    29    | DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK                                             | CLK_STATE_READY | 0               |
|   152     |    31    | DEV_DSS0_DPI0_EXT_CLKSEL                                                     | CLK_STATE_READY | 600000000       |
|   152     |    32    | DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK           | CLK_STATE_READY | 600000000       |
|   152     |    33    | DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT                  | CLK_STATE_READY | 0               |
|   152     |    34    | DEV_DSS0_DPI1_EXT_CLKSEL                                                     | CLK_STATE_READY | 600000000       |
|   152     |    35    | DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK           | CLK_STATE_READY | 600000000       |
|   152     |    36    | DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT                  | CLK_STATE_READY | 0               |
|-----------------------------------------------------------------------------------------------------------------------------------------|

-------------------------------------------------------------------------------------------------------------------------------------
*************************************************************************************************************************************
-------------------------------------------------------------------------------------------------------------------------------------
LIST of tested modes:


// DSI: htotal=2880, crtc_htotal=960, hs_clk=171,414Mhz hs_byte_clk=21.5Mhz,
// DSI: Dynamic REFCLK=12.2Mhz, idiv=2 ,odiv=8 ,fbdiv=286 fcalc= 171.600Mhz: OK;
// DSI: Static  REFCLK=19.2Mhz, idiv=2 ,odiv=8 ,fbdiv=286 fcalc= 171.600Mhz: OK;  
// DSI: Static  REFCLK=24Mhz,   idiv=2 ,odiv=8 ,fbdiv=229 fcalc= 171.750Mhz: OK;
&lvdspanel {
    panel-timing {
        clock-frequency = <28569600>;
        hactive = <800>;
        vactive = <480>;
        hsync-len = <32>;
        hfront-porch = <48>;
        hback-porch = <80>;
        vsync-len = <7>;
        vfront-porch = <3>;
        vback-porch = <6>;
    };
};

// DSI: htotal=3168, crtc_htotal=1056, hs_clk=240Mhz hs_byte_clk=30Mhz,
// DSI: DPI(HFP) > DSI(HSS+HSA+HSE+HBP) :: 38400000000 == 25920000000
// DSI: Dynamic REFCLK=24Mhz:   idiv=2,odiv=8,fbdiv=320 fcalc=240Mhz: Not working, TVG OK;
// DSI: Static  REFCLK=19.2Mhz, idiv=2,odiv=8,fbdiv=400 fcalc=240Mhz: Not working; TVG not tested;
// DSI: Static  REFCLK=24Mhz,   idiv=2,odiv=8,fbdiv=320 fcalc=240Mhz: Not working; TVG OK;
&lvdspanel {
    panel-timing {
        clock-frequency = <40000000>;
        hactive = <800>;
        vactive = <600>;
        hsync-len = <128>;
        hfront-porch = <40>;
        hback-porch = <88>;
        vsync-len = <4>;
        vfront-porch = <1>;
        vback-porch = <23>;
    };
};

// DSI: htotal=3840, crtc_htotal=1280, hs_clk=390Mhz hs_byte_clk=48.75Mhz,
// DSI: DPI(HFP) > DSI(HSS+HSA+HSE+HBP) :: 62400000000 == 42120000000
// DSI: Dynamic REFCLK=39Mhz:   idiv=4 ,odiv=4 ,fbdiv=320 fcalc=390Mhz: OK;
// DSI: Static  REFCLK=19.2Mhz, idiv=2 ,odiv=4 ,fbdiv=325 fcalc=390Mhz: OK;  
// DSI: Static  REFCLK=24Mhz,   idiv=2 ,odiv=4 ,fbdiv=260 fcalc=390Mhz: OK;
&lvdspanel {
    panel-timing {
        clock-frequency = <65000000>;
        hactive = <1024>;
        vactive = <768>;
        hsync-len = <136>;
        hfront-porch = <40>;
        hback-porch = <80>;
        vsync-len = <6>;
        vfront-porch = <3>;
        vback-porch = <29>;
    };
};


// DSI: htotal=4320, crtc_htotal=1440 hs_clk=445,5Mhz hs_byte_clk=55.6875Mhz,
// DSI: Dynamic REFCLK=44.55Mhz:  idiv=4,odiv=4,fbdiv=320 fcalc=445.5Mhz: Not working, TVG OK;
// DSI: Static  REFCLK=19.2Mhz,   idiv=2,odiv=4,fbdiv=372 fcalc=446.4Mhz: Not working; TVG OK;
&lvdspanel {
    panel-timing {
        clock-frequency = <74250000>;
        hactive = <1280>;
        vactive = <720>;
        hsync-len = <40>;
        hfront-porch = <112>;  // originaly <110>
        hback-porch = <220>;
        vsync-len = <5>;
        vfront-porch = <5>;
        vback-porch = <20>;
    };
};

// DSI: htotal=4320, crtc_htotal=1440, hs_clk=413.4Mhz hs_byte_clk=51.675Mhz, main18/hsdiv1=1584700000
// DSI: Dynamic REFCLK=41,34Mhz:  idiv=4,odiv=4,fbdiv=320 fcalc=413.4Mhz: OK;
// DSI: Static  REFCLK=19.2Mhz,   idiv=2,odiv=4,fbdiv=345 fcalc=413.4Mhz: OK - some shifts at LVDS side, not problem of DSI;  
// DSI: Static  REFCLK=24Mhz,     idiv=2,odiv=4,fbdiv=276 fcalc=413.4Mhz: OK - some shifts at LVDS side;
&lvdspanel {
    panel-timing {
        clock-frequency = <68900000>;
        hactive = <1280>;
        vactive = <800>;
        hsync-len = <80>;
        hfront-porch = <40>;
        hback-porch = <40>;
        vsync-len = <10>;
        vfront-porch = <3>;
        vback-porch = <10>;
    };
};

// DSI: htotal=5400, crtc_htotal=1800, hs_clk=515.196Mhz hs_byte_clk=64.3995Mhz, main18/hsdiv1=1545588000
// DSI: Dynamic REFCLK=51,5196Mhz: idiv=4 ,odiv=4 ,fbdiv=320  fcalc= 515.196Mhz: OK;
&lvdspanel {
    panel-timing {
        clock-frequency = <85866392>;
        hactive = <1368>;
        vactive = <768>;
        hsync-len = <144>;
        hfront-porch = <72>;
        hback-porch = <216>;
        vsync-len = <3>;
        vfront-porch = <1>;
        vback-porch = <23>;
    };
};


Kind regards,

David

  • Hi David,

    I have not used DSI output from Linux, but essentially link output speed should match with the input pixel clock, output format and number of output lanes. If there is any mismatch, it can create issue. So could you please make sure they are all matching? 

    Regards,

    Brijesh

  • Hi Brijesh,

    DSI is configured to use 4 lanes. Output format is the same for all resolutions - RGB888.

    Setting for sync pulse polarity is the same for all tested resolutions (negative hsyn and vsyn).

    I am quite sure that all clocks are matching - it could be seen from description

    example: 1368x768 pixclk=85866392hz --> which is rounded by the DRM to 85866000Hz, it leads to DSI HS byte clk = pixclk * 24 (RGB888) / 8 / 4 (lanes) = 64399500Hz --> DSI hs_bitclk = 515196000Hz

    All frequencies seems to be OK. But some resolutions works and some not ??? I can't find what is wrong, because all conditions are met for all cases.

  • Hi Robert,

    What's the fps that you are expecting? trying to understand how pixel clock for 1368x768 came to 85866392?

    Regards,

    Brijesh 

  • Hi Brijesh

    it was just a test, although this example is working.I have tested many resolutions, some of them are working and others not. I have tested many parameters settings - frequencies (DSI, DSS-DPI), HFP, HSA, HFP I am not found any correlation in parameters that should explain this behavior.

    I am expecting to bring alive my display with second resolution from report:

    // DSI: htotal=3168, crtc_htotal=1056, hs_clk=240Mhz hs_byte_clk=30Mhz,
    // DSI: DPI(HFP) > DSI(HSS+HSA+HSE+HBP) :: 38400000000 == 25920000000
    // DSI: Dynamic REFCLK=24Mhz:   idiv=2,odiv=8,fbdiv=320 fcalc=240Mhz: Not working, TVG OK;
    // DSI: Static  REFCLK=19.2Mhz, idiv=2,odiv=8,fbdiv=400 fcalc=240Mhz: Not working; TVG not tested;
    // DSI: Static  REFCLK=24Mhz,   idiv=2,odiv=8,fbdiv=320 fcalc=240Mhz: Not working; TVG OK;
    &lvdspanel {
        panel-timing {
            clock-frequency = <40000000>;
            hactive = <800>;
            vactive = <600>;
            hsync-len = <128>;
            hfront-porch = <40>;
            hback-porch = <88>;
            vsync-len = <4>;
            vfront-porch = <1>;
            vback-porch = <23>;
        };
    };

    TVG is working with this setting. All conditions for DSI are met. Driver doesn't report any issue, but data lines are at idle level.  I have tried fixed ref clock 24Mhz, 19.2Mhz as many other. Dynamic ref clk  is feature that I have added to the driver to set the best ref clk frequency for PLL. It seems that there is not problem with DSI PHY but somewhere between DSS-DPI and DSI I guess.

    flags for DPI  = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC

    flags for DSI = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_NO_EOT_PACKET

    also I have tested that with flags = MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP |
    MIPI_DSI_MODE_VIDEO_NO_HSA

  • Hi Robert,

    Can you please readback value of below register for non-working resolutions?

    Regards,

    Brijesh

  • Memory mapped at address 0xffff930a7000.
    Read at address  0x048000F0 (0xffff930a70f0): 0x00000004

  • That's missing hsync error. This is why it is not working.. 

    Can you please share the complete video timings for this case? 

    Regards,

    Brijesh

  • From panel setting:

    // DSI: htotal=3168, crtc_htotal=1056
    &lvdspanel {
        panel-timing {
            clock-frequency = <40000000>;
            hactive = <800>;
            vactive = <600>;
            hsync-len = <128>;
            hfront-porch = <40>;
            hback-porch = <88>;
            vsync-len = <4>;
            vfront-porch = <1>;
            vback-porch = <23>;
        };

    DSI :hs_clk=240Mhz hs_byte_clk=30Mhz, 

    DSI_PHY PLL :  REFCLK=24Mhz:   idiv=2,odiv=8,fbdiv=320 fcalculated=240Mhz

    &dphy2 {
       status = "okay";
       /delete-property/ assigned-clocks;
       /delete-property/ assigned-clock-parents;
       /delete-property/ assigned-clock-rates;
       assigned-clocks = <&k3_clks 296 3>;
       assigned-clock-parents = <&k3_clks 296 6>;
       assigned-clock-rates = <24000000>; // this can be changed in arbitrary way I tested 19.2Mhz as well
    };

    I have applied patch that allows to set system PLL at precise frequency so DPI pixel clock is exactly 40Mhz.

  • ok, when this usecase is running, can you please reducing HFP and BlkLinePulse fields in below register by equal amounts? start with 2, then 4 and then 6 and so. and see if any of the change is giving you correct output?

    Regards,

    Brijesh

  • Hi Brijesh,

    I have tried that - no success.

  • Hi Robert,

    Can you please confirm that you have tried changing both HFP and blank line pulse? also what all values have you tried with? 

    Regards,

    Brijesh

  • Hi Brijesh,

    I have added debug attributes to cdns driver, so I am able to change both values in more fancy way. I have tested 2,4,6,8,10 .... and so one up to 128 - no success.

    What I see on the scope is at the screenshot . First I see the transition from idle to HS for some time period (the length of that time period changes when I update HFP and BlkLinePulse). Then I see one frame sent. During VBLANK the data line is in iddle state. Then another frame started but after blanking the data line is stopped to the idle. Mising HSYNC is then reported as the error.

    Snippet from function: cdns_dsi_bridge_enable()

    writel(HFP_LEN(dsi_cfg.hfp - dsi->reduce) | HACT_LEN(dsi_cfg.hact),

    dsi->regs + VID_HSIZE2);

    writel(BLK_LINE_PULSE_PKT_LEN(tmp - dsi->reduce), dsi->regs + VID_BLKSIZE2);

    Correction: first window is just DSI reset - clock and data line are simply off.

    Another investigation:

    I suspect that driver set the content of DSI_VID_DPHY_TIME register in a bad way.

    Value REG_WAKEUP_TIME calculated by the driver is higher than 2^12 and it is finally cut.

    I have experimented with this value just setting this value low - and I got it.

    Actually I don't know how how to calculate right value - but I know pretty sure that driver do that in a bad way !!!!!!!

    An example is there: I have set REG_WAKEUP_TIME to (50) and DSI output looks that:

    And display is working !!!!

    So my question is: how to calculate the right wake-up time ?

    FIXED:

    in driver cdns-dsi-core.c in function cdns_dsi_bridge_enable()

    I have fixed wakeup time calculation, with updated formula it starts to work.

    Previous code mixed ps time units with ns time units that leads to bad value.

    I will prepare a patch after code cleanup (some debug ballast)

    updated code looks like that:

    static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)

    {

    .....
    unsigned long hs_clk_period; /*added*/
    .......
    tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8,

    phy_cfg->hs_clk_rate);

    hs_clk_period = DIV_ROUND_UP_ULL((u64)ALIGN(PSEC_PER_SEC, phy_cfg->hs_clk_rate),

    phy_cfg->hs_clk_rate); /*added*/

    reg_wakeup = (phy_cfg->hs_prepare + phy_cfg->hs_zero) / hs_clk_period; /*fixed*/

    writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp),

    dsi->regs + VID_DPHY_TIME);

    ....

  • Hi Robert,

    That's strange, at least in RTOS driver code, this parameter value is fixed to 0x1A8. 

    Let me check in the Linux code.

    Regards,

    Brijesh

  • Hi Brijesh,

    I have spent a lot of time just with scope and display. I am understand this parameter as the number of bit clocks (not byte) necessary to wait for change dataline from low power to high speed mode. But the original calculation in driver do that calculation with byte clock (I also tried that but it didn't work well - dsi output was unstable). But it can be seen from the code that they calculate together value derived from nano-seconds (tx_byte_period)  and values (phy_cfg->hs_prepare + phy_cfg->hs_zero) in pico-seconds and this leads to quite big values in result - bigger  than the register size is.

    When I tried the formula I suggested it starts to work.

    I have found another condition consequence - that it is necessary to have HS bit clock at precise multiply of reference clock, in other case the dsi output is unstable.

    When both (wait time and HS bit clock) conditions are met then DSI output is working and it is stable.

    I am able to set precise HS bit clock frequency both in DTB (calculate HS bit clock from pixel clock and divide by some reasonable number) or in the code of PHY driver (just setting reference clock as a multiple of HS clock). Of course in that case the source of reference clock must be set to PLL (MAIN_3_HSDIVOUT4_CLK or MAIN_2_HSDIVOUT4_CLK) instead of HFOSCx (that is fixed).

    I have found that dsi output works with some bigger values of wait time than I have calculated but in a strange way. Transition to LP lasted more time that just Vblank. It looks like that DSI tried to work but the timing was wrong. And more it was quite random - some resolution worked and other not.

    I will try fixed value from RTOS may it is in the range (the clock is the minimal wait time).

  • Hi Brijesh,

    I have spent a lot of time just with scope and display. I am understand this parameter as the number of bit clocks (not byte) necessary to wait for change dataline from low power to high speed mode. But the original calculation in driver do that calculation with byte clock (I also tried that but it didn't work well - dsi output was unstable). But it can be seen from the code that they calculate together value derived from nano-seconds (tx_byte_period)  and values (phy_cfg->hs_prepare + phy_cfg->hs_zero) in pico-seconds and this leads to quite big values in result - bigger  than the register size is.

    When I tried the formula I suggested it starts to work.

    I have found another condition consequence - that it is necessary to have HS bit clock at precise multiply of reference clock, in other case the dsi output is unstable.

    When both (wait time and HS bit clock) conditions are met then DSI output is working and it is stable.

    I am able to set precise HS bit clock frequency both in DTB (calculate HS bit clock from pixel clock and divide by some reasonable number) or in the code of PHY driver (just setting reference clock as a multiple of HS clock). Of course in that case the source of reference clock must be set to PLL (MAIN_3_HSDIVOUT4_CLK or MAIN_2_HSDIVOUT4_CLK) instead of HFOSCx (that is fixed).

    I have found that dsi output works with some bigger values of wait time than I have calculated but in a strange way. Transition to LP lasted more time that just Vblank. It looks like that DSI tried to work but the timing was wrong. And more it was quite random - some resolution worked and other not.

    I will try fixed value from RTOS may it is in the range (calculated value of wait time is actually the minimal wait time).

    FIXED VALUE TEST: yep with fixed value from RTOS (0x1a8) it is working.

  • Hi Robert,

    I have found another condition consequence - that it is necessary to have HS bit clock at precise multiply of reference clock, in other case the dsi output is unstable.

    Can you please elaborate more on this? What exactly did you have to make in the PHY driver to get it working or what changes are required in the dtb file to provide hs bit clock? I want to fix the issue properly in the driver. 

    Regards,

    Brijesh 

  • Hi Brijesh

    There is two possible ways how to set D-PHY reference clock in a desired way. First it is necessary to set system PLL as a source for reference clock, because in the original setting fixed oscillator is used. There is a snippet from DTB:

    &dphy2 {

    status = "okay";

    /delete-property/ assigned-clocks;

    /delete-property/ assigned-clock-parents;

    /delete-property/ assigned-clock-rates;

    assigned-clocks = <&k3_clks 296 3>;

    assigned-clock-parents = <&k3_clks 296 6>;

    assigned-clock-rates = <19200000>; // Reference clock (***) -- this need to be updated

    };

    Next it is necessary to set the reference clock to be divisible by integer from HS-bit-clock.

    -----------------

    First way it could be done in DTB:

    Let say that we use 4 lane configuration so HS bit clock can be calculated from pixel clock this way:

    HS-bit-clock = Pixel-clock * bpp (24 for RGB888) / num_lanes(4)

    Example of calculation:

    Let say that we have custom resolution of display:

    // VESA 1368 x 768 60Hz

    &custom_panel {

    panel-timing {

    clock-frequency = <85866392>; // this will be rounded by DRM to 85866000

    hactive = <1368>;

    vactive = <768>;

    hsync-len = <144>;

    hfront-porch = <72>;

    hback-porch = <216>;

    vsync-len = <3>;

    vfront-porch = <1>;

    vback-porch = <23>;

    };

    };

    so we have hs-bit-clock = 85866000 * 24 / 4 = 515196000

    This is not integer - divisible by 19200000 (ref clock) 515196000 / 19200000 = 28.833...

    So let the reference clock to be just hs-bit-clock / 10 =  51519600. This number is then placed to dtb as ref-clock:

    &dphy2 {

    ........

    assigned-clock-rates = <51519600>; // Reference clock (***) -- this need to be calculated

    };

    ---------------

    Or it is possible to little adjust D-PHY driver (drivers/phy/cadence/cdns-dphy.c) to calculate that.

    Code snippet is there:

    static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,

    struct cdns_dphy_cfg *cfg,

    struct phy_configure_opts_mipi_dphy *opts,

    unsigned int *dsi_hfp_ext)

    {

    unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk);

    u64 dlane_bps;

    //***************************************

    #ifdef CONFIG_PHY_CADENCE_EXACT_REFCLK

    int clkret;

    #endif

    //***************************************

    memset(cfg, 0, sizeof(*cfg));

    //***************************************

    #ifdef CONFIG_PHY_CADENCE_EXACT_REFCLK

    //set new ref rate:

    pll_ref_hz = DIV_ROUND_UP_ULL(opts->hs_clk_rate, CONFIG_PHY_CADENCE_REFCLK_RATIO);

    if (pll_ref_hz < 19200000) pll_ref_hz = 19200000; // minimal frequency is 18750000

    if (pll_ref_hz >= 150000000) pll_ref_hz = 149000000;

    dev_dbg(&dphy->phy->dev, "%s: new DSI-PHY PLL ref clk is - %lu \n", __func__, pll_ref_hz);

    clkret = clk_set_rate(dphy->pll_ref_clk, pll_ref_hz);

    dev_dbg(&dphy->phy->dev, "%s: setting new DSI-PHY PLL ref clk ret_val=%d \n", __func__, clkret);

    pll_ref_hz = clk_get_rate(dphy->pll_ref_clk);

    dev_dbg(&dphy->phy->dev, "%s: checked new DSI-PHY PLL ref clk is - %lu \n", __func__, pll_ref_hz);

    #endif

    //***************************************

    if (pll_ref_hz < 9600000 || pll_ref_hz >= 150000000)

    .........

    The code in gray boxes are addition. I added kernel config parameters for convenience. But CONFIG_PHY_CADENCE_REFCLK_RATIO is set to 8 by default.

    ------------------

    For completeness there is the fix in DSI bridge driver for LP-HS WAIT time calculation (drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c):

    static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)

    {

    ...
    unsigned long hs_clk_period;
    ......
    tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8, phy_cfg->hs_clk_rate);

    hs_clk_period = DIV_ROUND_UP_ULL((u64)ALIGN(PSEC_PER_SEC, phy_cfg->hs_clk_rate), phy_cfg->hs_clk_rate);

    reg_wakeup = (phy_cfg->hs_prepare + phy_cfg->hs_zero) / hs_clk_period;

    writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp), dsi->regs + VID_DPHY_TIME);

    .......

  • Hi David,

    Thanks for sharing this. I am taking this with our team and also trying to verify these requirements with the PHY team. Will update the driver once it is confirmed. 

    Regards,

    Brijesh