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TDA4AH-Q1: TDA4AH

Gang Liu
Prodigy 130 points
Part Number: TDA4AH-Q1

Hello,

I have a couple of questions about TDA4AH.

(1) There are 4 part numbers, are they sharing the same package and pin out? Are they all in production now?

XTDA4AHXXXGAALY

XTDA4APXXXGAALY

XTDA4VHXXXGAALY

XTDA4VPXXXGAALY

(2) I have a folder of schematic and layout, PROC141E4_RP.

Can you please help check whether it is the latest version? In the schematic, the chip is called XJ784S4GAALY or J7AHP, what does it mean?

  • 0
    TI__Mastermind 44420 points

    Yes, version E4 is the latest revision for PROC141.  Yes - all four devices have same package/pinout.  See the data manual section 4 (Device Comparison) for details on the differences of the devices. 

    https://www.ti.com/lit/gpn/tda4vh-q1

    J784S4 is a 'super-set' device referenced on EVMs - also referred to as J7AHP is some documentation.  The orderable parts are listed in the data manual.

  • 0 in reply to Robert Eschler
    Prodigy 130 points

    Hi Robert,

    Thanks for the reply.

    I have some SERDES 1-8 questions, please correct me if I am wrong, thanks.

    (1) From this we have 8 PORTs for xH chip, and my understanding is only QSGMII is different. If we plan to use QSGMII of 5G, then we can only have 2 physical ports available, one from PORT1-4, the other from PORT5-8. All the rest 6 ports are not functional.

    (2) For 1G/2.5G SGMII and 10G XFI/USXGMII, it does not occupy other ports. For example, I can have below config, and all 8 ports can work together(no QSGMII):

    P1 = 5G/10G XFI or 5G/10G USXGMII

    P2 = 5G/10G XFI or 5G/10G USXGMII

    P3-P8 = 1G/2.5G SGMII

    (3) For the pin mapping. SGMII1-8 are mapping to PORT1-PORT8 described above? Some SGMII is defined on one pin, some SGMII is shared by two pins, our software needs to define each pin for SGMII1-8, which is PORT1-PORT8.

  • 0 in reply to Gang Liu
    TI__Mastermind 44420 points

    Q1:  QSGMII does map 4x 1G SGMII ports to a single SERDES link.  Yes - could use 2x QSGMII to access all 8 1G ports.  There is some flexibility in programming which 4 ports are used in the QSGMII stream.  I think you program the first Port you want mapped, example SGMII3 - and it would take it and the next 3 ports enabled (so could be SGMII3, 4, 5, 6).  

    Q2:  Correct - only SGMII1 and SGMII2 support the higher data rates, SGMII3-8 support up to 2.5Gbps.

    Q3:  Yes - SGMII1 maps to Port 1.  Some ports are mapped to multiple pin locations.  For example, since SGMII1, 2 are the higher speed - these are available at couple different locations to give customer flexibility on how they assign the SERDES.

  • 0 in reply to Robert Eschler
    Prodigy 130 points

    Just to confirm on Q2, P1 and P2 5G or even 10G from XFI or USXGMII, does not prevent P3-P8 from working in 2.5G SGMII, is that true? Total BW can be 10*2 + 2.5G*6 = 35G?

    P1 = 5G/10G XFI or 5G/10G USXGMII

    P2 = 5G/10G XFI or 5G/10G USXGMII

    P3-P8 = 1G/2.5G SGMII

    I am not very familiar with QSGMII, from the physical wise is it x1 lane the same as SGMII? Or it require x4 lanes in physical?

  • +1 in reply to Gang Liu
    TI__Mastermind 44420 points

    Interfaces operate independently - so yes P1, P2 can operate at 5G/10G and it does not affect other ports.  (Note I'm just referring to SERDES ports, and not any internal processing that might be included in handling of ethernet traffic).

    QSGMII uses a single SERDES lane (similar to SGMII).  It operates at 5G speeds and carries 4x ports of 1Gb SGMII data.  So it behaves like 4x SGMII ports, but its just transmitted on single SERDES lane.