Other Parts Discussed in Thread: AM67
Hi,
Wit the AM67A, how does TI recommend we generate a PCIe RESET signal?.
thanks
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Hello Stephen,
Our expert who handles PCIe is on out of office till Apr 19th. Please expect reponse once he is back.
Thanks.
Hi Stephen,
If the purpose is to simulate taking out a PCIe add-in card and then re-enumerating, you can use commandline to:
Regards,
Takuma
Hi Takuma,
The purpose of generating the PERST- signal is to keep any PCIe peripherals in an reset state until the PCIe bus (i.e the AM67 SERDES) is up and running. With the J721e (which I'm familiar) this was done using a GPIO.
On further examination of the J722s EVM, I see that the reset is generated from a GPIO (GPIO Expander - 1 Part # TCA6424ARGJR - port P22 ). So I guess I just need to find where in the Linux PCIe driver this port is manipulated and translate that to my design (using a SoC GPIO port).
thanks
Hi Stephen,
Understood. To help you with your port, in our dts file, this line is where the PERST signal is connected to our driver: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-j722s-evm.dts?h=ti-linux-6.1.y#n877
And the expander is defined here: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-j722s-evm.dts?h=ti-linux-6.1.y#n451.
And it is consumed here: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/pci/controller/cadence/pci-j721e-host.c?h=ti-linux-6.1.y#n374.
Regards,
Takuma
Thanks - that helps a lot. Just to confirm that the j721e pcie host code is used in the J722s? (make sense as they are probably using the same PCIe peripheral block)