SK-AM68: Design Question

d_zero

Part Number: SK-AM68
Other Parts Discussed in Thread: SK-AM69, AM68A, AM68

Dear Team,

we have some questions regarding SK-AM68:

1) Do you maybe have and can provide the detailed time diagram for power-up sequence of SK-AM69? ( We are aware that there is a general diagram in AM68A datasheet for combined rails)

2) Do you have a measurement for the VDD_DDR_1V1_REG rail when 100% utilization of DDR0 and DDR1 channel?

-> in our design we want to remove DDR1 channel, and we would like to know how much power is left for use?

we want to use it for 1.1V FPDLinkIV Deser ( 1.6A max as per DS)

and check if the sequence is valid regarding the fpdlink deser requirement.

Best Regards,

over 2 years ago

0 Robert Eschler over 2 years ago

TI__Guru 56735 points

The attached shows the planned timing sequence. I think this was a preliminary document, but timing should be correct.

J721S2 SK Edge AI Flex Tulip PDN-6A v0.6.pdf

Here is link for the PMIC application note: https://www.ti.com/lit/pdf/slda060

Regarding the power estimate, the AM68 silicon page has link to power estimation spreadsheet (https://www.ti.com/lit/pdf/spruj91) and the memory datasheet should have max current for memory.

0 d_zero over 2 years ago in reply to Robert Eschler

Genius 5055 points

Hi Robert,

thank you for the document, please can you verify that the timing sequence is the correct and used in SK-AM68?

Also in the sequence the Timing Tu-1 is missing it says TBD, please can you provide this data?

Best Regards,

+1 Robert Eschler over 2 years ago in reply to d_zero

TI__Guru 56735 points

Yes - the timing sequence is correct. Looking at measurements, looks like timing between Tu-1 and Tu0 is 6ms.

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SK-AM68: Design Question